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SL811HS Datasheet(PDF) 25 Page - Cypress Semiconductor |
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SL811HS Datasheet(HTML) 25 Page - Cypress Semiconductor |
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25 / 32 page ![]() SL811HS Document 38-08008 Rev. *F Page 25 of 32 Bus Interface Timing Requirements I/O Write Cycle Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns minimum. nWR A0 D0-D7 DATA twr twahld twdhld twasu twdsu twdsu twdhld I/O Write Cycle to Register or Memory Buffer Register or Memory Address nCS twcsu twshld Tcscs See Note. twrhigh Parameter Description Min Typ Max tWR Write pulse width 85 ns tWCSU Chip select set-up to nWR LOW 0 ns tWSHLD Chip select hold time After nWR HIGH 0 ns tWASU A0 address set-up time 85 ns tWAHLD A0 address hold time 10 ns tWDSU Data to Write HIGH set-up time 85 ns tWDHLD Data hold time after Write HIGH 5 ns tCSCS nCS inactive to nCS* asserted 85 ns tWRHIGH NWR HIGH 85 ns [+] Feedback |
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