SL811HS

Document 38-08008 Rev. *F

Page 22 of 32

Figure 6. Package Markings (48-Pin TQFP)

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

33

BIDIR

D6

Data 6. Microprocessor Data/Address Bus.

34

NC

NC

No connection.

35

NC

NC

No connection.

36

NC

NC

No connection.

37

NC

NC

No connection.

38

NC

NC

No connection.

39

BIDIR

D7

Data 7. Microprocessor Data/Address Bus.

40

IN

M/S

Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master.

41

VDD

+3.3 VDC

42[8]

IN

A0

A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data buffer or

register.

43

IN

nDACK

DMA Acknowledge. An active LOW input used to interface to an external

DMA controller. DMA is enabled only in slave mode. In host mode, the pin

should be tied HIGH (logic ’1’).

44

OUT

nDRQ

DMA Request. An active LOW output used with an external DMA controller.

nDRQ and nDACK form the handshake for DMA data transfers. In host

mode, leave the pin unconnected.

45

IN

nRD

Read Strobe Input. An active LOW input used with nCS to read

registers/data memory.

46

NC

NC

No connection.

47

NC

NC

No connection.

48

NC

NC

No connection.

Table 34. Pin and Signal Description for Pins

48-Pin TQFP

AXC Pin No.

Pin Type

Pin Name

Pin Description

Notes

7. VDD can be derived from the USB supply. Figure 5 on page 20 shows a simple method to provide 3.3 V/30 mA. Another option is to use a Torex Semiconductor,

Ltd. 3.3 V SMD regulator (part number XC62HR3302MR).

8. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.

Part Number

YYW W -X.X

XXXX

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