71M6543F datasheet(67/157 Pages) MAXIM

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71M6543F/H and 71M6543G/GH Data Sheet

v1.2

2.5.11.2 Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin

A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is

selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are

shown in Table 56. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM

or read from the EEPROM, depending on the values of the EECTRL bits.

2.5.11.3 Three-Wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins

If DIO_EEX[1:0] = 11, the 71M6543 three-wire interface is the same as above, except DI and DO are

separate pins. In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams

are the same as for DIO_EEX[1:0] = 10 except that all output data appears on DO and all input data is

expected on DI. In this mode, DI is ignored while data is being received on DO. This mode is compatible

with SPI modes 0,0 and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on

the rising edge of the clock.

Table 56: EECTRL Bits for the 3-wire Interface

Control

Bit

Name

Read/

Write

Description

WFR

Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until

a rising edge is seen on the data line. This bit can be used during the

last byte of a Write command to cause the INT5 interrupt to occur when

the EEPROM has finished its internal write sequence. This bit is

ignored if HiZ=0.

BUSY

Asserted while the serial data bus is busy. When the BUSY bit falls, an

INT5 interrupt occurs.

HiZ

Indicates that the SD signal is to be floated to high impedance immediately

after the last SDCK rising edge.

Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.

3:0

CNT[3:0]

Specifies the number of clocks to be issued. Allowed values are 0

through 8. If RD = 1, CNT bits of data are read MSB first, and right

justified into the low order bits of EEDATA. If RD = 0, CNT bits are sent

MSB first to the EEPROM, shifted out of the MSB of EEDATA. If

CNT[3:0] is zero, SDATA simply obeys the HiZ bit.

The timing diagrams in Figure 18 through Figure 22 describe the 3-wire EEPROM interface behavior. All

commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that

is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 18 through Figure 22

are then sent via EECTRL and EEDATA.

When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM

drives SDATA, but transitions to HiZ (high impedance) when CS falls. The firmware should then

immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a

low-Z state.

Figure 18: 3-wire Interface. Write Command, HiZ=0.

SCLK (output)

BUSY (bit)

CNT Cycles (6 shown)

SDATA (output)

Write -- No HiZ

EECTRL Byte Written

INT5

SDATA output Z

(LoZ)

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