71M6543F datasheet(35/157 Pages) MAXIM

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71M6543F/H and 71M6543G/GH Data Sheet

v1.2

Table 14: Port Registers (SEGDIO0-15)

SFR

Name

SFR

Address

DIO_DIR[3:0]

DIO[3:0]

DIO_DIR[7:4]

DIO[7:4]

DIO_DIR[11:8]

DIO[11:8]

DIO_DIR[15:12]

DIO[15:11]

All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output

driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if

a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when

counting pulses issued via DIO pins that are under CE control.

At power-up SEGDIO0-15 are configured as inputs. It is necessary to write PORT_E = 1 (I/O

RAM 0x270C[5]) to enable SEGDIO0-DIO15. The default PORT_E = 0 blocks any momentary

output transient pulses that would otherwise occur when SEGDIO0-15 are reset on power-up.

Clock Stretching (CKCON[2:0], SFR 0x8E)

The CKCON[2:0] field defines the stretch memory cycles that are used for MOVX instructions when

accessing external peripherals. The practical value of this register for the 71M6543 is to guarantee access

to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should be changed to 000

for best performance.

Table 15 shows how the signals of the External Memory Interface change when stretch values are set

from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the

CKCON[2:0] field (001), which is shown in bold in the table, performs the MOVX instructions with a

stretch value equal to 1.

Table 15: Stretch Memory Cycle Width

CKCON[2:0]

Stretch

Value

Read Signal Width

Write Signal Width

memaddr

memrd

memaddr

memwr

000

001

010

011

100

101

110

111

2.4.4

Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set

and of the associated op-codes is contained in the 71M654x Software User’s Guide (SUG).

2.4.5

80515 Power Reduction Modes

The 80515 core provides two power reduction modes: Idle Mode and Power-Down Mode. These power

saving modes are invoked by setting the appropriate control bit in the PCON SFR register (SFR 0x87).

Idle Mode halts the MPU while allowing the interrupt, timer, and serial port functions to continue to

operate. Once Idle Mode has been entered, an interrupt event automatically ends Idle Mode. After the

interrupt has been serviced, program execution continues with the instruction immediately following the

instruction that set the Idle Mode bit. To enter Idle Mode, the firmware must set the IDL bit (bit 0) in the

PCON SFR register (SFR 0x87).

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