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71M6543F Datasheet(PDF) 44 Page - Maxim Integrated Products |
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71M6543F Datasheet(HTML) 44 Page - Maxim Integrated Products |
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44 / 157 page  71M6543F/H and 71M6543G/GH Data Sheet 44 © 2008–2011 Teridian Semiconductor Corporation v1.2 IP1(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling sequence as shown in Table 37 determines which request is serviced first. Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best to set the interrupt priority registers only once during initialization before interrupts are enabled. Table 35: Interrupt Priority Levels IP1[x] IP0[x] Priority Level 0 0 Level 0 (lowest) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest) Table 36: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) IP0 SFR 0xA9 – – IP0[5] IP0[4] IP0[3] IP0[2] IP0[1] IP0[0] IP1 SFR 0xB9 – – IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] IP1[0] |
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