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71M6543F Datasheet(PDF) 62 Page - Maxim Integrated Products |
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71M6543F Datasheet(HTML) 62 Page - Maxim Integrated Products |
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62 / 157 page ![]() 71M6543F/H and 71M6543G/GH Data Sheet 62 © 2008–2011 Teridian Semiconductor Corporation v1.2 LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] (I/O RAM 0x2443[5:0] to 0x2447[5:0]) DIO Data Register 51 52 53 54 55 – – – LCD_SEGDIO51[0] to LCD_SEGDIO55[0] (I/O RAM 0x2443[0] to 0x2447[0]) Direction Register: 0 = input, 1 = output 51 52 53 54 55 – – – LCD_SEGDIO51[1] to LCD_SEGDIO55[1] (I/O RAM 0x2443[1] to 0x2447[1]) 2.5.10.3 LCD Drivers The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers. The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols. A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from a trimmed low-power reference. The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM 0x2401[7:6]). It is decoded into LCD_EXT, LDAC_E, and LCD_BSTE. Table 52 details the LCD_VMODE[1:0] configurations. |
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