ADATE318 datasheet(68/80 Pages) AD

68 / 80 page

ADATE318

Rev. 0 | Page 68 of 80

GAIN AND OFFSET CORRECTION

Each DAC within the ADATE318 has independent gain (m)

and offset (c) correction registers that allow digital trim of gain

and offset errors. DACs that are shared between functions or

levels are provided with per-level or per-function gain and

offset correction registers, as appropriate. These registers

provide the ability to calibrate out errors in the complete signal

chain, which includes error in pin electronics function as well as

the DACs. All m- and c-registers are volatile and must be

loaded after power-on as part of a calibration cycle if values

other than the defaults are required.

The gain and offset correction function can be bypassed by

clearing the DAC_CAL_ENABLE bit in the SPI DAC contol

is available on a per-chip basis only; that is, it is not possible to

bypass calibration for a subset of the DACs.

The calibration function, when enabled, adjusts the numerical

data sent to each DAC according to the following equation:

1





























 



where:

X2 = the data-word loaded into the DAC and returned by an SPI

read operation.

X1 = the 16-bit data-word written to the DAC SPI input register.

m = the code in the respective DAC gain register (default code

= 0xFFFF = 2n − 1).

c = the code in the respective DAC offset register (default code

= 0x8000 = 2n−1).

n = the DAC resolution (n = 16).

From this equation, it can be seen that the gain applied to the X1

value is always less than or equal to 1.0, with the effect that a

DAC’s output voltage can only be made smaller. To compensate

for this numerically imposed limitation, the ADATE318’s signal

paths are designed to have gain guaranteed to be greater than

1.0 when the default m values (0xFFFF) are applied. This

guarantees that proper gain calibration is always possible. Note

also that the value of c is expressed in raw DAC LSBs; that is, it

is calculated without considering the effect of the m-register.

When enabled, the calibration function applies the above

operation to the X2 register(s) only after a SPI write to the

respective X1 register(s). The X2 registers are not updated after

writes to either the m- or c-register. In the case of a dual

channel write to the DAC, two respective X2 registers are

sequentially updated using the appropriate m and c values.

X2 REGISTERS

Each DAC has associated with it a single X2 register. There is no

provision for storing separate X2 values for DACs shared

between functions or ranges. Thus, new data must be written to

any shared DAC after a mode or range change is performed,

even if the old and new DAC data is identical. The ADATE318

provides separate m- and c-registers for all ranges and modes so

that the new X2 value is calculated correctly following the new

data write, provided the desired m and c values are stored in

advance. The sequence of operations is critical in that the mode

or range change must be performed prior to writing the new

DAC data, and both m and c values must be present before the

new DAC data is written. The m and/or c value can be written

either before or after a mode or range change but must be

written prior to the DAC data to have the intended effect.

SAMPLE CALCULATIONS OF M AND C

Because the ADATE318’s on-chip DACs have a theoretical

output range that exceeds the operating capabilities of the

remainder of its signal channels, calibration points must be

chosen to be within the normal operating span. Subject to this

constraint, calibration is straightforward. One of the keys to

understanding the calibration method is to recognize that the

intrinsic DAC offset is defined by its output when the input

code is 0x0000. This is quite different from the case of the

analog signal paths, where a 0 V level occurs when the DAC

code is programmed to near quarter-scale.

As a first example, consider the calibration of a drive high level

with a theoretical output span of −2.5 V to 7.5 V, a convenient

10.0 V span in which DAC quarter-scale corresponds to

precisely 0.0 V out. The ADATE318 drivers do not of course

support this full span, but it is a useful choice for illustration of

the calibration methodology.

Set the channel to drive high and program the VIL and

VIT DACs for roughly −1.0 V outputs (Code 0x2700, not

critical). Program the VIH DAC to quarter-scale (0x4000)

and measure Output Voltage V1; then program the DAC to

three-quarter-scale (0xC000) and measure Output Voltage

V2. Note that V1 and V2 should be measured with respect to

DUTGND.

Calculate



FSR

DAC

Actual







where (V2 − V1) represents half the full-scale span.

Calculate the extrapolated DAC voltage at Code 0x0000.

















FSR

DAC

Actual

Calculate





768

LSB

DAC

Actual





Calculate



536





















Calculate the offset from the ideal −2.5 V.





Offset





ADATE318 Datasheet(PDF) 68 Page - Analog Devices

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