ADATE318 datasheet(22/80 Pages) AD

Part #	ADATE318

Description	600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip

PDF	80 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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22 / 80 page

ADATE318

Rev. 0 | Page 22 of 80

SPI TIMING DETAILS

SCLK

SDI

D15 D14

6789

1234567

D15 D14

SDO

BUSY

tCH

tCL

tCSAS

tCSAH

tCSO

tDS

tDH

tDO

tCSAM

tCSRS

tCSRH

tCSZ

tBUSA

tBUSR

tBUSW

SEE TABLE 18

NOTE 1

NOTES

1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE

FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE

SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.

R/W

Figure 2. SPI Detailed Read/Write Timing Diagram

SCLK

SDI

SDO

BUSY

FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18)

SEE TABLE 18

CH[1:0]

ADDR[6:0]

DATA[15:0]

NOTE 1

ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI

NOTES

1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE

FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE

SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS.

Figure 3. SPI Write Instruction

ADATE318 Datasheet(PDF) 22 Page - Analog Devices

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