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ADATE318 Datasheet(PDF) 69 Page - Analog Devices

Part # ADATE318
Description  600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip
PDF  80 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADATE318 Datasheet(HTML) 69 Page - Analog Devices

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ADATE318
Rev. 0 | Page 69 of 80
7.
Calculate


LSB
DAC
Actual
Offset
c
_
_
768
,
32
8.
Calculate volts


1
2
5
_
_
_
_
_
V
V
LSB
DAC
Actual
LSB
DAC
n
Calibratio
Post
The above procedure places the DAC’s theoretical 0x0000
output at −2.5 V and its theoretical 0xFFFF output at 7.49985 V
(1 LSB below +7.5 V). The useful range extends from below
0x199A (−1.5 V) to above 0xE666 (+6.5 V), a span of at least
52,428 actual DAC codes.
An alternative calibration approach can be used to map all 216
DAC codes onto the part’s specified output range by mapping
the zero-code to −1.5 V and the full-scale code to +6.5 V.
1.
Repeat Step 1 to Step 4 above.
2.
Calculate

535
,
65
4
1
2
V
V
m
3.
Calculate the offset from the desired −1.5 V.
0
5
.
1
V
Offset
4.
Calculate DAC


LSB
DAC
Actual
Offset
c
_
_
768
,
32
5.
Calculate
536
,
65
8
_
_
_
LSB
DAC
n
Calibratio
Post
Volts
Although this second approach gives an apparent 16 bits of
resolution covering the full signal range, it must be kept in
mind that this is achieved purely by mathematical alteration of
the DAC data. The DAC’s internal LSB step size is not changed.
In this example, the number of internal DAC codes used to
cover the signal span remains roughly 52,428 even though the
number of user codes has increased to 65,536. A consequence
of this is that apparent DNL errors are increased as more input
codes are mapped onto the same number of DAC codes. While
the second calibration method is included here as an example of
what is possible, its use can provide a false sense of improved
accuracy and it is therefore not recommended.



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