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ADATE318 Datasheet(PDF) 19 Page - Analog Devices

Part # ADATE318
Description  600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip
PDF  80 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADATE318 Datasheet(HTML) 19 Page - Analog Devices

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ADATE318
Rev. 0 | Page 19 of 80
Parameter
Min
Typ
Max
Unit
Test
Level
Conditions
Comparator Uncertainty Band
1.6
mV
CB
Sweep comparator threshold to determine
uncertainty (oscillation) band
DC Hysteresis
<1
mV
CB
Sweep comparator threshold
COMPARATOR OUTPUTS
PPMU_CMPHx, PPMU_CMPLx
Output Logic High
VDD/4
− 0.5
VDD/4
+ 0.5
V
PF
Sourcing 100 μA
Output Logic Low
0
0.5
V
PF
Sinking 100 μA
Table 9. PPMU_Sense Pin
Parameter
Min
Typ
Max
Unit
Test
Level
Condition
PMU_Sx (SYSTEM PMU)
SENSE PIN CHARACTERISTICS
Voltage Range
−2.0
+7.0
V
D
DCL high-Z compliance range is −2.0 V to
+7.0 V
Ext Sense Switch RON
2.5
kΩ
P
Push 0.5 mA into PMU_Sx with switch closed
and DUTx pin at 0 V; calculate R = V/0.0005
Leakage
−2
+2
nA
P
Tested at −2.0 V and +7.0 V, switch open
Pin Capacitance (PMU_Sx)
0.5
pF
S
Switch open
PPMU_Sx (INTERNAL PPMU)
SENSE PIN CHARACTERISTICS
Voltage Range
−2.0
+6.5
V
D
PPMU input select in all states
Leakage
−2
+2
nA
P
Tested at −2.0 V and
+6.5 V
Max Load Capacitance
2
nF
S
Table 10. Serial Programmable Interface (SPI) (SDI, RST, CS, SCLK, SDO, BUSY)
Parameter
Min
Typ
Max
Unit
Test
Level
Condition
Input Logic High
1.8
VCC
V
PF
SDI, RST, CS, SCLK.
Input Logic Low
0
0.7
V
PF
Input Bias Current
−10
±1
+10
μA
P
Tested at 0.0 V and
VCC volts.
SCLK Clock Rate
0.5
50
MHz
D
SCLK Pulse Width, Minimum
9
ns
CT
SCLK Crosstalk on DUTx Pin
30
mV
CB
DCL disabled; PPMU FV enabled and forcing
0.0 V.
Serial Output Logic High
VCC − 0.5
VCC
V
PF
SDO; sourcing 2 mA.
Serial Output Logic Low
0
0.5
V
PF
Sinking 2 mA.
BUSY Pull-Up Voltage
2.3
2.5
3.5
V
D
BUSY is an open drain output that pulls low
when the SPI requires additional SCLK cycles.
BUSY Active Voltage
0.2
0.8
V
PF
BUSY active, sinking 2 mA.



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