TPS62361BYZHT datasheet(28/52 Pages) TI

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Data line stable;

data valid

Change of

data allowed

SDA

SCL

START condition

Clock Pulse for

Acknowledgment

Data Output

by Transmitter

SCL

Not Acknowledge

Acknowledge

Data Output

by Receiver

TPS62360, TPS62361B, TPS62362

SLVSAU9A

– MAY 2011 – REVISED AUGUST 2011

www.ti.com

the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

Figure 42. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the

addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

Figure 43. Acknowledge on the I2C Bus

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TPS62361BYZHT Datasheet(PDF) 28 Page - Texas Instruments