TPS62361BYZHT datasheet(29/52 Pages) TI

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START or

repeated START

Condition

Clock Line Held Low While

Interrupts are Serviced

SCL

ACK

2-8

ACK

Recognize START or

repeated START

Condition

Acknowledgment

Signal From Slave

SDA

Generate ACKNOWLEDGE

Signal

repeated START

or STOP

Condition

Recognize

repeated START

or STOP

Condition

Address

Data

From TPS6236x to Master

From Master to TPS6236x

Acknowledge

START condition

REPEATED START condition

STOP condition

Slave Address

R/W

Slave Address

“0” Write

“1” Read

Slave Address

R/W

Slave Address

R/W

Data

From TPS6236x to Master

From Master to TPS6236x

Acknowledge

START condition

REPEATED START condition

STOP condition

TPS62360, TPS62361B, TPS62362

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SLVSAU9A

– MAY 2011 – REVISED AUGUST 2011

Figure 44. Bus Protocol

HS-Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of

the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be

used to secure the bus in HS-mode.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

2C UPDATE SEQUENCE

The TPS6236x requires a start condition, a valid I2C address, a register address byte, and a data byte for a

single update. After the receipt of each byte, the TPS6236x device acknowledges by pulling the SDA line low

during the high period of a single clock pulse. A valid I2C address selects the TPS6236x. The TPS6236x

performs an update on the falling edge of the acknowledge signal that follows the LSB byte.

Figure 45. Write Data Transfer Format in F/S-Mode

Figure 46. Read Data Transfer Format in F/S-Mode

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