TPS62361BYZHT datasheet(33/52 Pages) TI

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AVIN

VOUT

VDD

VIN

AGND

PGND

TPS62360, TPS62361B, TPS62362

www.ti.com

SLVSAU9A

– MAY 2011 – REVISED AUGUST 2011

The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at TJ = 105°C) is affected by

the junction temperature and the continuously drawn current at the VIN pin and the SW pins. In order to be

consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at TJ = 105°C), the

VIN pin current should not continuously exceed 1275mA and the SW pins current should not continuously

exceed 2550mA so as to prevent electromigration failure in the solder bump. Drawing 1150mA at VIN would, as

an example, be the case for typically IOUT = 2350mA, VOUT = 1.5V and VIN = 3.6V.

Exceeding the VIN pin / SW pins current rating might affect the device reliability. As an example, drawing current

peaks IOUT = 3000mA with up to 10% of the application time over a base continuous output current IOUT =

2000mA might reduce the Power-on-Hours to 90000 hours for conditions such as VIN = 2.7V, VOUT = 1.5V, TJ =

105

°C. In this example, exceeding TJ = 105°C in combination with a higher peak output current duty cycle clearly

further affects the device life time.

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics

Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953).

PCB LAYOUT CONSIDERATIONS

The PCB layout is an important step to maintain the high performance of the TPS6236x. Both the high current

and the fast switching nodes demands full attention to the PCB layout.

The input / output capacitors and the inductor should be placed as close as possible to the IC. This keeps the

traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance. A

common power GND should be used. The low side of the input and output capacitors must be connected to the

power GND, as well as the PGND node. AGND and PGND should be connected close to the IC but at a single

place.

The sense traces connected to SENSE+ and SENSE- are signal traces. Special care should be taken to avoid

noise being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used for

shielding if the parasitic capacitance can be kept small. Routing the SENSE+ and SENSE- close to each other

minimizes inductive noise injection. Keep these traces away from switching nodes and swiftly alternating signal

lines such as the I2C bus.

Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts,

stability issues or unsatisfying EMI behavior.

See Figure 48 for the recommended layout.

Figure 48. Layout Suggestion (top view). Overall Solution Size: 27.5mm2

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Product Folder Link(s): TPS62360 TPS62361B TPS62362

TPS62361BYZHT Datasheet(PDF) 33 Page - Texas Instruments

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