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AM3871 Datasheet(PDF) 196 Page - Texas Instruments |
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AM3871 Datasheet(HTML) 196 Page - Texas Instruments |
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196 / 345 page  AM3874, AM3872, AM3871 SPRS695 – SEPTEMBER 2011 www.ti.com Table 7-25. Maximum SYSCLK Clock Frequencies (continued) MAX CLOCK FREQUENCY SYSCLK OPP100 (MHz) SYSCLK4 200 SYSCLK5 RSV SYSCLK6 100 SYSCLK7 RSV SYSCLK8 192 SYSCLK9 RSV SYSCLK10 48 SYSCLK11 RSV SYSCLK12 RSV SYSCLK13 RSV SYSCLK14 27 SYSCLK15 RSV SYSCLK16 27 SYSCLK17 RSV SYSCLK18 0.32768 SYSCLK19 192 SYSCLK20 192 SYSCLK21 192 SYSCLK22 RSV SYSCLK23 200 7.4.8 Module Clocks Device Modules either receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 7-26 lists the clock source options for each Module on this device, along with the maximum frequency that Module can accept. To ensure proper Module functionality, the device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table. Table 7-26. Maximum Module Clock Frequencies MAX FREQUENCY MODULE CLOCK SOURCE(S) OPP100 (MHz) PLL_ARM Cortex-A8 600 SYSCLK18 DCAN0/1 DEV Clock 30 DDR0/1 PLL_DDR 400 DMM PLL_DDR/2 200 EDMA SYSCLK4 200 EMAC Switch (GMII) SATA SERDES Fixed 125 PLL_VIDEO0 PLL_VIDEO1 EMAC Switch (RGMII) Fixed 250 PLL_VIDEO02 PLL_L3 SATA SERDES EMAC Switch (RMII and MII) Fixed 50 EMAC_RMREFCLK Pin GPIO SYSCLK6 100 GPIO Debounce SYSCLK18 Fixed 0.032768 GPMC SYSCLK6 100 HDMI PLL_VIDEO2 186 HDMI CEC SYSCLK10 Fixed 48 196 Power, Reset, Clocking, and Interrupts Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3874 AM3872 AM3871 |
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