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AM3871 Datasheet(PDF) 38 Page - Texas Instruments

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Part # AM3871
Description  AM387x Sitara ARM Microprocessors (MPUs)
PDF  345 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3871 Datasheet(HTML) 38 Page - Texas Instruments

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AM3874, AM3872, AM3871
SPRS695
– SEPTEMBER 2011
www.ti.com
Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2) (3)
DESCRIPTION
NAME
NO.
DDR[0] On-Die Termination for Chip Select 0.
IPD/DIS
DDR[0]_ODT[0]
G18
O
The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] On-Die Termination for Chip Select 1.
IPD/DIS
DDR[0]_ODT[1]
H19
O
The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
DDR[0] Reset output
IPD/DIS
DDR[0]_RST
G19
O
The internal pulldown (IPD) is enabled for this pin when the device is
DVDD_DDR[0]
in reset and the IPD is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_BA[2]
A18
O
DVDD_DDR[0]
DDR[0] Bank Address outputs
IPU/DIS
DDR[0]_BA[1]
A20
O
The internal pullup (IPU) is enabled for these pins when the device is
DVDD_DDR[0]
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_BA[0]
F15
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[14]
F16
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[13]
F17
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[12]
E17
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[11]
D17
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[10]
A19
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[9]
C15
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[8]
B15
O
DVDD_DDR[0]
DDR[0] Address Bus
IPU/DIS
DDR[0]_A[7]
E18
O
The internal pullup (IPU) is enabled for these pins when the device is
DVDD_DDR[0]
in reset and the IPU is disabled (DIS) when reset is released.
IPU/DIS
DDR[0]_A[6]
A15
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[5]
B17
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[4]
D15
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[3]
E15
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[2]
D18
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[1]
F19
O
DVDD_DDR[0]
IPU/DIS
DDR[0]_A[0]
B19
O
DVDD_DDR[0]
38
Device Pins
Copyright
© 2011, Texas Instruments Incorporated
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