AM3871 datasheet(93/345 Pages) TI1

93 / 345 page

AM3874, AM3872, AM3871

www.ti.com

SPRS695

– SEPTEMBER 2011

3.2.13 PCI Express (PCIe)

Table 3-24. PCI Express (PCIe) Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

DESCRIPTION

NAME

NO.

PCIE_TXP0

AD2

PCIE Transmit Data Lane 0.

–

When the PCIe SERDES are powered down, these pins should be

VDDA_PCIE_1P8

PCIE_TXN0

AD1

left unconnected.

PCIE_RXP0

AC2

PCIE Receive Data Lane 0.

–

When the PCIe SERDES are powered down, these pins should be

VDDA_PCIE_1P8

PCIE_RXN0

AC1

left unconnected.

–

PCIE Serdes Reference Clock Inputs and optional SATA

SERDES_CLKP

AF1

SERDES_CLK LDO

Reference Clock Inputs.

(internal)

Shared between PCI Express and Serial ATA. When PCI Express

–

is not used, and these pins are not used as optional SATA

SERDES_CLKN

AF2

SERDES_CLK LDO

Reference Clock Inputs, these pins can be left unconnected.

(internal)

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2)

IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown

resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3)

Specifies the operating I/O supply voltage for each signal

Device Pins

Submit Documentation Feedback

Product Folder Link(s): AM3874 AM3872 AM3871

AM3871 Datasheet(PDF) 93 Page - Texas Instruments

AM3871 Datasheet(HTML) 93 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL