AM3871 datasheet(12/345 Pages) TI1

12 / 345 page

AM3874, AM3872, AM3871

SPRS695

– SEPTEMBER 2011

www.ti.com

2.6

SGX530 Overview

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications.

The SGX530 graphics accelerator efficiently processes a number of various multimedia data types

concurrently:

•

Pixel data

•

Vertex data

•

Video data

This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning

enabling zero overhead task switching.

The SGX530 has the following major features:

•

Vector graphics and 3D graphics

•

Tile-based architecture

•

Universal Scalable Shader Engine (USSE

™) - multi-threaded engine incorporating pixel and vertex

shader functionality

•

Advanced shader feature set - in excess of Microsoft VS3.0, PS3.0, and OpenGL2.0

•

Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1

•

Fine-grained task switching, load balancing, and power management

•

Advanced geometry DMA driven operation for minimum CPU interaction

•

Programmable high-quality image anti-aliasing

•

POWERVR SGX core MMU for address translation from the core virtual address to the external

physical address (up to 4GB address range)

•

Fully-virtualized memory addressing for OS operation in a unified memory architecture

•

Advanced and standard 2D operations [e.g., vector graphics, block level transfers (BLTs), raster

operations (ROPs)]

For more details on the Secure State Machine (SSM), see the System MMU section of the Chip Level

Resources chapter of the AM387x Sitara ARM Microprocessors (MPUs) Technical Reference Manual

(Literature Number: SPRUGZ7).

2.7

Spinlock Module Overview

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple

processors in the device:

•

ARM Cortex-A8 processor

•

Media Controller

The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to

perform a lock operation of a device resource using a single read-access, avoiding the need for a

read-modify-write bus transfer of which the programmable cores are not capable.

For more details on the Spinlock Module, see the Spinlock section of the Chip Level Resources chapter of

the AM387x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (Literature Number:

SPRUGZ7).

Device Overview

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