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AM3871 Datasheet(PDF) 37 Page - Texas Instruments |
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AM3871 Datasheet(HTML) 37 Page - Texas Instruments |
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37 / 345 page  AM3874, AM3872, AM3871 www.ti.com SPRS695 – SEPTEMBER 2011 3.2.4 LPDDR/DDR2/DDR3 Memory Controller Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. LPDDR/DDR2/DDR3 Memory Controller 0 (DDR[0]) DDR[0] Clock IPD/DIS DDR[0]_CLK B16 O The internal pulldown (IPD) is enabled for this pin when the device is DVDD_DDR[0] in reset and the IPD is disabled (DIS) when reset is released. DDR[0] Negative Clock IPU/DIS DDR[0]_CLK A16 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. IPD DDR[0]_CKE H18 O DDR[0] Clock Enable DVDD_DDR[0] DDR[0] Write Enable IPU/DIS DDR[0]_WE C17 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. DDR[0] Chip Select 0 IPU/DIS DDR[0]_CS[0] F18 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. DDR[0] Chip Select 1 IPU/DIS DDR[0]_CS[1] G17 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. DDR[0] Row Address Strobe output IPU/DIS DDR[0]_RAS B18 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. DDR[0] Column Address Strobe output IPU/DIS DDR[0]_CAS C18 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[0] reset and the IPU is disabled (DIS) when reset is released. IPU DDR[0]_DQM[3] F20 O DDR[0] Data Mask outputs DVDD_DDR[0] DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24] IPU DDR[0]_DQM[2]: For DDR[0]_D[23:16] DDR[0]_DQM[2] C24 O DVDD_DDR[0] DDR[0]_DQM[1]: For DDR[0]_D[15:8] DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0] IPU DDR[0]_DQM[1] B28 O DVDD_DDR[0] The internal pullup (IPU) is enabled for these pins when the device is IPU in reset and switches to an IPD enabled when reset is released. DDR[0]_DQM[0] E28 O DVDD_DDR[0] IPD DDR[0]_DQS[3] B21 I/O DVDD_DDR[0] Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when IPD DDR[0]_DQS[2] B23 I/O reading. They are used to synchronize the data transfers. DVDD_DDR[0] DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] IPD DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1] B26 I/O DVDD_DDR[0] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] IPD DDR[0]_DQS[0] D28 I/O DVDD_DDR[0] IPU DDR[0]_DQS[3] A21 I/O Complimentary data strobe input/outputs for each byte of the 32-bit DVDD_DDR[0] data bus. They are outputs to the DDR[0] memory when writing and IPU inputs when reading. They are used to synchronize the data DDR[0]_DQS[2] A23 I/O DVDD_DDR[0] transfers. DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] IPU DDR[0]_DQS[1] A26 I/O DDR[0]_DQS[2]: For DDR[0]_D[23:16] DVDD_DDR[0] DDR[0]_DQS[1]: For DDR[0]_D[15:8] IPU DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] DDR[0]_DQS[0] D27 I/O DVDD_DDR[0] (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State (2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset. (3) Specifies the operating I/O supply voltage for each signal Copyright © 2011, Texas Instruments Incorporated Device Pins 37 Submit Documentation Feedback Product Folder Link(s): AM3874 AM3872 AM3871 |
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