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AM3871 Datasheet(PDF) 20 Page - Texas Instruments

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Part # AM3871
Description  AM387x Sitara ARM Microprocessors (MPUs)
PDF  345 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3871 Datasheet(HTML) 20 Page - Texas Instruments

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AM3874, AM3872, AM3871
SPRS695
– SEPTEMBER 2011
www.ti.com
Cortex-A8 and L3 Masters
SIZE
DEVICE NAME
START ADDRESS
END ADDRESS
(HEX)
(HEX)
0x4824_0000
0x4824_0FFF
4KB
MPUSS config register(1)
0x4824_1000
0x4827_FFFF
252KB
Reserved(1)
0x4828_0000
0x4828_0FFF
4KB
SSM(1)
0x4828_1000
0x482F_FFFF
508KB
Reserved(1)
0x4830_0000
0x48FF_FFFF
13MB
Reserved
2.9.3
DDR DMM TILER Extended Addressing Map
The Tiler includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access
the frame buffer in rotated and mirrored views. shows the details of the Tiler Extended Address Mapping.
This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However,
other masters can access any one single view through the 512-MB Tiler region in the base 4GByte
address memory map.
Table 2-6. DDR DMM TILER Extended Address Mapping
START ADDRESS
END ADDRESS
BLOCK NAME
SIZE
DESCRIPTION
(HEX)
(HEX)
Tiler View 0
0x1 0000_0000
0x1 1FFF_FFFF
512MB
Natural 0
° View
Tiler View 1
0x1 2000_0000
0x1 3FFF_FFFF
512MB
0
° with Vertical Mirror
View
Tiler View 2
0x1 4000_0000
0x1 5FFF_FFFF
512MB
0
° with Horizontal Mirror
View
Tiler View 3
0x1 6000_0000
0x1 7FFF_FFFF
512MB
180
° View
Tiler View 4
0x1 8000_0000
0x1 9FFF_FFFF
512MB
90
° with Vertical Mirror
View
Tiler View 5
0x1 A000_0000
0x1 BFFF_FFFF
512MB
270
° View
Tiler View 6
0x1 C000_0000
0x1 DFFF_FFFF
512MB
90
° View
Tiler View 7
0x1 E000_0000
0x1 FFFF_FFFF
512MB
90
° with Horizontal Mirror
View
20
Device Overview
Copyright
© 2011, Texas Instruments Incorporated
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Product Folder Link(s): AM3874 AM3872 AM3871



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