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AM3871 Datasheet(PDF) 41 Page - Texas Instruments |
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AM3871 Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 345 page  AM3874, AM3872, AM3871 www.ti.com SPRS695 – SEPTEMBER 2011 Table 3-5. LPDDR/DDR2/DDR3 Memory Controller 1 Terminal Functions SIGNAL TYPE(1) OTHER(2) (3) DESCRIPTION NAME NO. LPDDR/DDR2/DDR3 Memory Controller 1 (DDR[1]) DDR[1] Clock IPD/DIS DDR[1]_CLK B13 O The internal pulldown (IPD) is enabled for this pin when the device is DVDD_DDR[1] in reset and the IPD is disabled (DIS) when reset is released. DDR[1] Negative Clock IPU/DIS DDR[1]_CLK A13 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. IPD DDR[1]_CKE H11 O DDR[1] Clock Enable DVDD_DDR[1] DDR[1] Write Enable IPU/DIS DDR[1]_WE E12 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. DDR[1] Chip Select 0 IPU/DIS DDR[1]_CS[0] G12 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. DDR[1] Chip Select 1 IPU/DIS DDR[1]_CS[1] G11 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. DDR[1] Row Address Strobe output IPU/DIS DDR[1]_RAS C12 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. DDR[1] Column Address Strobe output IPU/DIS DDR[1]_CAS F13 O The internal pullup (IPU) is enabled for this pin when the device is in DVDD_DDR[1] reset and the IPU is disabled (DIS) when reset is released. IPU/IPD DDR[1]_DQM[3] G9 O DDR[1] Data Mask outputs DVDD_DDR[1] DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24] IPU/IPD DDR[1]_DQM[2]: For DDR[1]_D[23:16] DDR[1]_DQM[2] G8 O DVDD_DDR[1] DDR[1]_DQM[1]: For DDR[1]_D[15:8] DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0] IPU/IPD DDR[1]_DQM[1] B2 O DVDD_DDR[1] The internal pullup (IPU) is enabled for these pins when the device is IPU/IPD in reset and switches to an IPD enabled when reset is released. DDR[1]_DQM[0] F4 O DVDD_DDR[1] IPD DDR[1]_DQS[3] B8 I/O DVDD_DDR[1] Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. IPD DDR[1]_DQS[2] A6 I/O They are used to synchronize the data transfers. DVDD_DDR[1] DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] IPD DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1] B3 I/O DVDD_DDR[1] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] IPD DDR[1]_DQS[0] D1 I/O DVDD_DDR[1] IPU/IPD Complimentary data strobe input/outputs for each byte of the 32-bit DDR[1]_DQS[3] A8 I/O DVDD_DDR[1] data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers. IPU/IPD DDR[1]_DQS[2] B6 I/O DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DVDD_DDR[1] DDR[1]_DQS[2]: For DDR[1]_D[23:16] IPU/IPD DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[1] A3 I/O DVDD_DDR[1] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] IPU/IPD The internal pullup (IPU) is enabled for these pins when the device is DDR[1]_DQS[0] D2 I/O DVDD_DDR[1] in reset and switches to an IPD enabled when reset is released. DDR[1] On-Die Termination for Chip Select 0. IPD/DIS DDR[1]_ODT[0] H10 O The internal pulldown (IPD) is enabled for this pin when the device is DVDD_DDR[1] in reset and the IPD is disabled (DIS) when reset is released. (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-selected Input State (2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset. (3) Specifies the operating I/O supply voltage for each signal Copyright © 2011, Texas Instruments Incorporated Device Pins 41 Submit Documentation Feedback Product Folder Link(s): AM3874 AM3872 AM3871 |
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