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LPC1850 Datasheet(PDF) 145 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 145 Page - NXP Semiconductors |
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145 / 157 page ![]() LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 3 — 6 December 2011 145 of 157 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller Conditions: Tamb = 25 C; normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 53. Typical supply current versus regulator supply voltage VDD(REG)(3V3) in active mode Conditions: VDD(REG)(3V3) = 3.0 V, normal mode entered executing code while(1){} from ROM; internal pull-up resistors disabled; system PLL enabled; IRC enabled, BOD disabled; all peripherals disabled; all peripheral clocks disabled. Fig 54. Typical supply current versus temperature in active mode 002aag121 VDD(REG)(3V3) (V) 2.0 3.6 3.2 2.8 2.4 12 MHz 36 MHz 60 MHz 84 MHz 132 MHz 144 MHz 108 MHz 20 40 60 IDD(REG)(3V3) (mA) 0 temperature (°C) -40 85 35 10 60 -15 002aag122 20 40 60 IDD(REG)(3V3) (mA) 0 12 MHz 36 MHz 84 MHz 144 MHz 108 MHz 60 MHz 132 MHz |
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