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AM3359 Datasheet(PDF) 152 Page - Texas Instruments

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Part # AM3359
Description  AM335x ARM짰 Cortex??A8 Microprocessors (MPUs)
PDF  195 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3359 Datasheet(HTML) 152 Page - Texas Instruments

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A1
A1
A
T
AM335x
AM335x
A1
DQ[0]
DQ[1]
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717B
– OCTOBER 2011 – REVISED JANUARY 2012
www.ti.com
5.4.2.2.3 DDR2 CK and ADDR_CTRL Routing
Figure 5-39 shows the topology of the routing for the CK and ADDR_CTRL net classes. The length of
signal path AB and AC should be minimized with emphasis to minimize lengths C and D such that length
A is the majority of the total length of signal path AB and AC.
Figure 5-39. CK and ADDR_CTRL Routing and Topology
Table 5-47. CK and ADDR_CTRL Routing Specification(1)(2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
Center-to-center CK spacing
2w
2
CK differential pair skew length mismatch(2)(3)
25
mils
3
CK B-to-CK C skew length mismatch
25
mils
4
Center-to-center CK to other DDR2 trace spacing(4)
4w
5
CK/ADDR_CTRL nominal trace length(5)
CACLM-50
CACLM
CACLM+50
mils
6
ADDR_CTRL-to-CK skew length mismatch
100
mils
7
ADDR_CTRL-to-ADDR_CTRL skew length mismatch
100
mils
8
Center-to-center ADDR_CTRL to other DDR2 trace spacing(4)
4w
9
Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing(4)
3w
10
ADDR_CTRL A-to-B/ADDR_CTRL A-to-C skew length mismatch(2)
100
mils
11
ADDR_CTRL B-to-C skew length mismatch
100
mils
(1) CK represents the clock net class, and ADDR_CTRL represents the address and control signal net class.
(2) Series terminator, if used, should be located closest to the AM335x device.
(3) Differential impedance should be Zo x 2, where Zo is the single-ended impedance defined in Table 5-39.
(4) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 5-40 shows the topology and routing for the DQS[x] and DQ[x] net classes; the routes are point to
point. Skew matching across bytes is not needed nor recommended.
Figure 5-40. DQS[x] and DQ[x] Routing and Topology
152
Peripheral Information and Timings
Copyright
© 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352



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