AM3359 datasheet(154/195 Pages) TI

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DDR_CK

DDR_CKn

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

www.ti.com

5.4.2.3

DDR3 Routing Guidelines

5.4.2.3.1 Board Designs

TI only supports board designs utilizing DDR3 memory that follow the guidelines in this document. The

switching characteristics and timing diagram for the DDR3 memory interface are shown in Table 5-49 and

Figure 5-41.

Table 5-49. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory

Interface

NO.

PARAMETER

MIN

MAX

UNIT

tc(DDR_CK/DDR_CKn) Cycle time, DDR_CK/DDR_CKn

3.3

3.3(1)

(1) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 memory devices.

Therefore, all standard-speed bin DDR3 memory devices are required to operate at 303 MHz.

Figure 5-41. DDR3 Memory Interface Clock Timing

5.4.2.3.1.1 DDR3 versus DDR2

This specification only covers AM335x PCB designs that utilize DDR3 memory. Designs using DDR2

memory should use the DDR2 routing guidleines described in Section 5.4.2.2. While similar, the two

memory systems have different requirements. It is currently not possible to design one PCB that meets

the requirements of both DDR2 and DDR3.

5.4.2.3.2 DDR3 Device Combinations

Since there are several possible combinations of device counts and single-side or dual-side mounting,

Table 5-50 summarizes the supported device configurations.

Table 5-50. Supported DDR3 Device Combinations

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(1)

(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

5.4.2.3.3 DDR3 Interface

5.4.2.3.3.1 DDR3 Interface Schematic

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used. Figure 5-42

shows the schematic connections for 16-bit interface on AM335x device using one x16 DDR3 device and

Figure 5-43 shows the schematic connections for 16-bit interface on AM335x device using two x8 DDR3

devices. The AM335x DDR3 memory interface only supports 16-bit wide mode of operation. The AM335x

device can only source one load connected to the DQS[x] and DQ[x] net class signals and two loads

connected to the CK and ADDR_CTRL net class signals. For more information related to net classes, see

Section 5.4.2.3.3.8.

154

Peripheral Information and Timings

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Product Folder Link(s): AM3359 AM3358 AM3357 AM3356 AM3354 AM3352

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