AM3359 datasheet(157/195 Pages) TI

157 / 195 page

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

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SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

5.4.2.3.3.2 Compatible JEDEC DDR3 Devices

Table 5-51 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.

Generally, the DDR3 interface is compatible with DDR3-800 devices in the x8 or x16 widths.

Table 5-51. Compatible JEDEC DDR3 Devices (Per Interface)

NO.

PARAMETER

MIN

MAX

UNIT

JEDEC DDR3 device speed grade(1)

DDR3-800

JEDEC DDR3 device bit width

x16

Bits

JEDEC DDR3 device count(2)

Devices

(1) DDR3 speed grade depends on desired clock rate. Data rate is 2x the clock rate. For DDR3-800, the clock rate is 400 MHz.

(2) For valid DDR3 device configurations and device counts, see Section 5.4.2.3.3.1, Figure 5-42, and Figure 5-43.

5.4.2.3.3.3 PCB Stackup

The minimum stackup for routing the DDR3 interface is a four-layer stack up as shown in Table 5-52.

Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal

integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

Table 5-52. Minimum PCB Stackup(1)

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Split Power Plane

Signal

Bottom signal routing

(1)

All signals that have critical signal integrity requirements should be

routed first on layer 1. It may not be possible to route all of these

signals on layer 1 which requires some to be routed on layer 4.

When this is done, the signal routes on layer 4 should not cross

splits in the power plane.

Peripheral Information and Timings

157

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