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WM8352 Datasheet(PDF) 203 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 203 Page - Wolfson Microelectronics plc |
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203 / 336 page  Production Data WM8352 w PD, February 2011, Rev 4.4 203 24.3.6 GPIO INTERRUPTS The first-level GP_INT interrupt comprises several second-level interrupts for the 13 GPIO pins. Each of these has a status bit in Register R30 and a mask bit in Register R35, as defined in Table 148. ADDRESS BIT LABEL DESCRIPTION R30 (1Eh) GPIO Interrupt Status 12 GP12_EINT GPIO12 interrupt. (Trigger controlled by GP12 registers.) Note: This bit is cleared once read. 11 GP11_EINT GPIO11 interrupt. (Trigger controlled by GP11 registers.) Note: This bit is cleared once read. 10 GP10_EINT GPIO10 interrupt. (Trigger controlled by GP10 registers.) Note: This bit is cleared once read. 9 GP9_EINT GPIO9 interrupt. (Trigger controlled by GP9 registers.) Note: This bit is cleared once read. 8 GP8_EINT GPIO8 interrupt. (Trigger controlled by GP8 registers.) Note: This bit is cleared once read. 7 GP7_EINT GPIO7 interrupt. (Trigger controlled by GP7 registers.) Note: This bit is cleared once read. 6 GP6_EINT GPIO6 interrupt. (Trigger controlled by GP6 registers.) Note: This bit is cleared once read. 5 GP5_EINT GPIO5 interrupt. (Trigger controlled by GP5 registers.) Note: This bit is cleared once read. 4 GP4_EINT GPIO4 interrupt. (Trigger controlled by GP4 registers.) Note: This bit is cleared once read. 3 GP3_EINT GPIO3 interrupt. (Trigger controlled by GP3 registers.) Note: This bit is cleared once read. 2 GP2_EINT GPIO2 interrupt. (Trigger controlled by GP2 registers.) Note: This bit is cleared once read. 1 GP1_EINT GPIO1 interrupt. (Trigger controlled by GP1 registers.) Note: This bit is cleared once read. 0 GP0_EINT GPIO0 interrupt. (Trigger controlled by GP0 registers.) Note: This bit is cleared once read. R38 (26h) GPIO Interrupt Mask 12:0 “IM_” + name of respective bit in R30 Interrupt mask. 0 = Do not mask interrupt. 1 = Mask interrupt. Each bit in R38 enables or masks the corresponding bit in R30. The default value for these bits is 0 (unmasked). Table 148 GPIO Interrupts |
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