WM8352 datasheet(206/336 Pages) WOLFSON

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WM8352

Production Data

PD, February 2011, Rev 4.4

206

ADDRESS

BIT

LABEL

DESCRIPTION

CHG_VBATT_LT_3P9_EINT

Battery Voltage < 3.9 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

CHG_VBATT_LT_3P1_EINT

Battery voltage < 3.1 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

CHG_VBATT_LT_2P85_EIN

Battery voltage < 2.85 interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

R33 (21h)

Interrupt Status

1 Mask

15:9

2:0

“IM_” + name of respective

bit in R25

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Each bit in R33 enables or masks the

corresponding bit in R25. The default

value for these bits is 0 (unmasked).

Table 152 Charger Interrupts

24.3.11 USB INTERRUPTS

The first-level USB_INT interrupt comprises one second-level interrupt for the USB limit switch. This

status bit is in Register R26 and its mask bit is in Register R34, as defined in Table 153.

ADDRESS

BIT

LABEL

DESCRIPTION

R26 (1Ah)

Interrupt

Status 2

USB_LIMIT_EINT

USB Limit Switch interrupt.

(Rising Edge triggered)

Note: This bit is cleared once read.

R34 (22h)

Interrupt

Status 2 Mask

IM_USB_LIMIT_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

When IM_USB_LIMIT_EINT is set to 1,

then USB_LIMIT_EINT in R26 does not

trigger an USB_INT interrupt when set.

The default value is 0 (unmasked).

Table 153 USB Interrupt

WM8352 Datasheet(PDF) 206 Page - Wolfson Microelectronics plc

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