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WM8352 Datasheet(PDF) 220 Page - Wolfson Microelectronics plc |
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WM8352 Datasheet(HTML) 220 Page - Wolfson Microelectronics plc |
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220 / 336 page  WM8352 Production Data w PD, February 2011, Rev 4.4 220 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 11:10 RSTB_TO[1:0] 11 Time that the /RST pin and /MEMRST output is held low after the chip reaches the active state. 00 = 15ms 01 = 30ms 10 = 60ms 11 = 120ms Default held in metal mask. 9 BG_SLEEP 0 Bandgap sleep mode 0 = never in sleep mode 1 = sleep mode is controlled by Main SM Default held in metal mask. 7 WDOG_DEBUG 0 Halts watchdog timer for system debugging 0 = normal operation 1 = WDOG halt Protected by security key. 6 CHIP_RESET_ENA 0 [No description available] Reset by state machine. 5 MEM_VALID 0 Indicates that the contents of external memory are still valid. This bit is cleared on startup and whenever /MEMRST is asserted from the main state machine. The system software should set this bit once the external memory has been set up. Controlled in hibernate mode by MEMRST_HIB_MODE 0 = External memory is not valid and needs restoring. 1 = External memory is valid. Reset when /MEMRST is asserted. 4 CHIP_SET_UP 0 A spare register bit that can be used by the system to say if the chip has been configured. It is reset by POR. 3 ON_DEB_T 0 ON pin Shutdown function debounce time 0 = 10s 1 = 5s Protected by security key. 1 ON_POL 1 ON pin polarity: 0 = Active high (ON) 1 = Active low (/ON) Protected by security key. Reset by state machine. Default held in metal mask. 0 IRQ_POL 0 IRQ pin polarity: 0 = Active low (/IRQ) 1 = Active high (IRQ) Reset by state machine. Default held in metal mask. Register 03h System Control 1 |
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