WM8352 datasheet(243/336 Pages) WOLFSON

243 / 336 page

Production Data

WM8352

PD, February 2011, Rev 4.4

243

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

Reset by state machine.

IM_WKUP_GP_WAKEUP_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Reset by state machine.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R40 (28h)

Clock

Control 1

TOCLK_ENA

Slow clock enable. Used for both the jack insert

detect debounce circuit and the zero cross timeout.

0 = slow clock disabled

1 = slow clock enabled

TOCLK_RATE

Slow Clock Selection (Used for volume update

timeouts and for jack detect debounce)

0 = SYSCLK / 2^21 (Slower Response)

1 = SYSCLK / 2^19 (Faster Response)

MCLK_SEL

Selects source for SYSCLK to CODEC

0 = MCLK pin

1 = FLL

MCLK_DIV

Selects MCLK division in slave (MCLK input) mode:

0 = divide MCLK by 1

1 = divide MCLK by 2

7:4

BCLK_DIV[3:0]

0100

Sets BCLK rate for Master mode

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0101 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 32

1111 = SYSCLK / 32

2:0

OPCLK_DIV[2:0]

000

OPCLK Frequency (GPIO function)

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 5.5

101 = SYSCLK / 6

110 = Reserved

111 = Reserved

WM8352 Datasheet(PDF) 243 Page - Wolfson Microelectronics plc

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