CY8C54LP datasheet(105/117 Pages) CYPRESS

105 / 117 page

PRELIMINARY

PSoC® 5LP: CY8C54LP Family

Datasheet

Document Number: 001-84934 Rev. **

Page 105 of 117

11.8.5 SWD Interface

Figure 11-68. SWD Interface Timing

11.8.6 TPIU Interface

Table 11-68. SWD Interface AC Specifications[60]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_SWDCK

SWDCLK frequency

3.3 V

≤ VDDD ≤ 5V

–

12[62]

MHz

1.71 V

≤ VDDD < 3.3 V

–

7[62]

MHz

1.71 V

≤ VDDD < 3.3 V, SWD over

USBIO pins

––

5.5[62]

MHz

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold

SWDIO input hold after SWDCK high

T = 1/f_SWDCK max

T/4

–

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

–

T/2

T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max

–

SW D IO

(PSoC input)

SW DCK

T_SW D I_setup

SW D IO

(PSoC output)

(1/f_SW DCK)

T_SW D I_hold

T_SW D O _valid

T_SW D O _hold

Notes

59. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU.

60. Based on device characterization (Not production tested).

61. f_TCK must also be no more than 1/3 CPU clock frequency.

62. f_SWDCK must also be no more than 1/3 CPU clock frequency.

63. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see “GPIO AC Specifications” on page 70.

Table 11-69. TPIU Interface AC Specifications[60]

Parameter

Description

Conditions

Min

Typ

Max

Units

TRACEPORT (TRACECLK) frequency

–

33[63]

MHz

SWV bit rate

–

33[63]

Mbit

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