AD7707 datasheet(31/40 Pages) AD

31 / 40 page

REV. A

AD7707

–31–

AD7707 to 8051 Interface

An interface circuit between the AD7707 and the 8XC51

microcontroller is shown in Figure 22. The diagram shows the

minimum number of interface connections with CS on the

AD7707 hard-wired low. In the case of the 8XC51 interface the

minimum number of interconnects is just two. In this scheme,

the DRDY bit of the Communications Register is monitored to

determine when the Data Register is updated. The alternative

scheme, which increases the number of interface lines to three,

is to monitor the DRDY output line from the AD7707. The

monitoring of the DRDY line can be done in two ways. First,

DRDY can be connected to one of the 8XC51’s port bits (such

as P1.0) which is configured as an input. This port bit is then

polled to determine the status of DRDY. The second scheme is

to use an interrupt-driven system, in which case the DRDY

output is connected to the INT1 input of the 8XC51. For inter-

faces that require control of the CS input on the AD7707, one

of the port bits of the 8XC51 (such as P1.1), which is config-

ured as an output, can be used to drive the CS input. The

8XC51 is configured in its Mode 0 serial interface mode. Its

serial interface contains a single data line. As a result, the

DATA OUT and DATA IN pins of the AD7707 should be

connected together with a 10 k

Ω pull-up resistor. The serial

clock on the 8XC51 idles high between data transfers. The

8XC51 outputs the LSB first in a write operation, while the

AD7707 expects the MSB first so the data to be transmitted has

to be rearranged before being written to the output serial regis-

ter. Similarly, the AD7707 outputs the MSB first during a read

operation while the 8XC51 expects the LSB first. Therefore, the

data read into the serial buffer needs to be rearranged before

the correct data word from the AD7707 is available in the

accumulator.

RFS

ADSP-2103/

ADSP-2105

RESET

SCLK

DATA OUT

DATA IN

AD7707

VDD

TFS

SCLK

Figure 23. AD7707 to ADSP-2103/ADSP-2105 Interface

AD7707 to ADSP-2103/ADSP-2105 Interface

Figure 23 shows an interface between the AD7707 and the

ADSP-2103/ADSP-2105 DSP processor. In the interface

shown, the DRDY bit of the Communications Register is again

monitored to determine when the Data Register is updated. The

alternative scheme is to use an interrupt-driven system, in which

case the DRDY output is connected to the IRQ2 input of the

ADSP-2103/ADSP-2105. The serial interface of the ADSP-

2103/ADSP-2105 is set up for alternate framing mode. The

RFS and TFS pins of the ADSP-2103/ADSP-2105 are config-

ured as active low outputs and the ADSP-2103/ADSP-2105

serial clock line, SCLK, is also configured as an output. The CS

for the AD7707 is active when either the RFS or TFS outputs

from the ADSP-2103/ADSP-2105 are active. The serial clock

rate on the ADSP-2103/ADSP-2105 should be limited to

3 MHz to ensure correct operation with the AD7707.

CODE FOR SETTING UP THE AD7707

Table XVII gives a set of read and write routines in C code for

interfacing the 68HC11 microcontroller to the AD7707. The

sample program sets up the various registers on the AD7707

and reads 1000 samples from the part into the 68HC11. The

setup conditions on the part are exactly the same as those out-

lined for the flowchart of Figure 20. In the example code given

here, the DRDY output is polled to determine if a new valid

word is available in the data register.

The sequence of the events in this program are as follows:

1. Write to the Communications Register, selecting channel one

as the active channel and setting the next operation to be a

write to the clock register.

2. Write to Clock Register setting the CLK DIV bit which

divides the external clock internally by two. This assumes

that the external crystal is 4.9512 MHz. The update rate is

selected to be 50 Hz.

3. Write to Communication Register selecting Channel 1 as the

active channel and setting the next operation to be a write to

the Setup Register.

4. Write to the Setup Register, setting the gain to 1, setting

bipolar mode, buffer off, clearing the filter synchronization

and initiating a self-calibration.

5. Poll the DRDY output.

6. Read the data from the Data Register.

7. Loop around doing Steps 5 and 6 until the specified number

of samples have been taken from the selected channel.

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