REV. A

AD7707

–32–

Table XVIII. C Code for Interfacing AD7707 to 68HC11

/* This program has read and write routines for the 68HC11 to interface to the AD7707 and the sample program sets the various

registers and then reads 1000 samples from one channel. */

#include <math.h>

#include <io6811.h>

#define NUM_SAMPLES 1000 /* change the number of data samples */

#define MAX_REG_LENGTH 2 /* this says that the max length of a register is 2 bytes */

Writetoreg (int);

Read (int,char);

char *datapointer = store;

char store[NUM_SAMPLES*MAX_REG_LENGTH + 30];

void main ()

{

/* the only pin that is programmed here from the 68HC11 is the /CS and this is why the PC2 bit of PORTC is made as an output */

char a;

DDRC = 0x04; /* PC2 is an output the rest of the port bits are inputs */

PORTC | = 0x04; /* make the /CS line high */

Writetoreg (0x20); /* Active Channel is AIN1/LOCOM, next operation as write to the clock register */

Writetoreg (0x18); /* master clock enabled, 4.9512MHz Clock, set output rate to 50Hz*/

Writetoreg (0x10); /* Active Channel is AIN1/LOCOM, next operation as write to the setup register */

Writetoreg (0x40); /* gain = 1, bipolar mode, buffer off, clear FSYNC and perform a Self Calibration*/

while (PORTC and 0x10); /* wait for /DRDY to go low */

for (a=0;a<NUM_SAMPLES;a++);

{

Writetoreg (0x38); /*set the next operation for 16 bit read from the data register */

Read (NUM_SAMPES,2);

}

}

Writetoreg (int byteword);

{

int q;

SPCR = 0x3f;

SPCR = 0X7f; /* this sets the WiredOR mode (DWOM=1), Master mode (MSTR=1), SCK idles high (CPOL=1), /SS can be low

always (CPHA=1), lowest clock speed (slowest speed which is master clock /32 */

DDRD = 0x18; /* SCK, MOSI outputs */

q = SPSR;

q = SPDR; /* the read of the staus register and of the data register is needed to clear the interrupt which tells the user that the data

transfer is complete */

PORTC &= 0xfb; /* /CS is low */

SPDR = byteword; /* put the byte into data register */

while (! (SPSR & 0x80)); /* wait for /DRDY to go low */

PORTC |= 0x4; /* /CS high */

}

Read (int amount, int reglength)

{

int q;

SPCR = 0x3f;

SPCR = 0x7f; /* clear the interupt */

DDRD = 0x10; /* MOSI output, MISO input, SCK output */

while (PORTC & 0x10); /* wait for /DRDY to go low */

PORTC & 0xfb ; /* /CS is low */

for (b=0;b<reglength;b++)

{

SPDR = 0;

while (! (SPSR & 0x80)); /* wait until port ready before reading */

*datapointer++=SPDR; /* read SPDR into store array via datapointer */

}

PORTC|=4; /* /CS is high */

}