AD9851 datasheet(7/23 Pages) AD

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AD9851

–7–

REV. C

REF

CLOCK

PHASE

DIFFERENCE

8-BIT DATA BUS

FQ UD

RESET

W CLK

AD9851

IOUT

AD9851

W CLK

FQ UD

RESET

IOUT

RESET

FQ UD

RESET

FQ UD

W CLK #2

W CLK #1

MICROPROCESSOR

MICROCONTROLLER

W CLK #2

W CLK #1

Figure 7. Application Showing Synchronization of Two

AD9851 DDSs to Form a Quadrature Oscillator

After a common RESET command is issued, separate W_CLKs

allow independent programming of each AD9851 40-bit input

FQ_UD pulse is issued after programming is completed to

simultaneously engage both oscillators at their specified fre-

quency and phase.

AD9851

IOUT

30MHz

CLOCK

BANDPASS

FILTER

FUNDAMENTAL

FCLK

IMAGE

FC – FO

IMAGE

FC + FO

120

180

240

FREQUENCY – MHz

240

FREQUENCY – MHz

IMAGE

FC + FO

BANDPASS

FILTER

AMPLIFIER

240MHz

AD9851

SPECTRUM

FINAL OUTPUT

SPECTRUM

Figure 8. Deriving a High Frequency Output Signal from

the AD9851 by Using an “Alias” or Image Signal

Differential DAC output connection (Figure 9) for reduction of

common-mode signals and to allow highly reactive filters to be

driven without a filter input termination resistor (see above

single-ended example, Figure 8). A 6 dB power advantage is

obtained at the filter output as compared with the single-ended

example, since the filter need not be doubly terminated.

REFERENCE

CLOCK

FILTER

DIFFERENTIAL

TRANSFORMER-COUPLED

OUTPUT

1:1 TRANSFORMER

i.e., MINI-CIRCUITS T1–1T

AD9851

DDS

Figure 9. Differential DAC Output Connection for Reduc-

tion of Common-Mode Signals

The AD9851 RSET input being driven by an external DAC

(Figure 10) to provide amplitude modulation or fixed, digital

amplitude control of the DAC output current. Full description

of this application is found as a “Technical Note” on the AD9851

web page (site address is www.analog.com) under “Related

Information.” An Analog Devices application note for the

AD9850, AN-423, describes another method of amplitude

control using an enhancement-mode MOSFET that is equally

applicable to the AD9851.

NOTE: If the 6

× REFCLK Multiplier of the AD9851 is en-

gaged, the 125 MHz clocking source shown in Figure 10 can be

reduced by a factor of six.

AD9851

DDS

DIFFERENTIAL

TRANSFORMER-COUPLED

OUTPUT

1:1 TRANSFORMER

IOUT

RSET

+5V

200

330

+5V

20mA

MAX

10-BIT DAC

AD9731

+5V

–5V

125MHz

10 BITS

DATA

GENERATOR

e.g., DG-2020

COMPUTER

CONTROL

DATA

Figure 10. The AD9851 RSET Input Being Driven by an External DAC

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