AD9851 datasheet(20/23 Pages) AD

20 / 23 page

AD9851

–20–

REV. C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2AP

1.1MHz

CENTER

200kHz

SPAN

20kHz/

RBW = 300Hz

VBW = 300Hz

SWT = 11.5s

RF ATT = 20dB

REF LVL = –7dBm

Figure 29. Narrowband (1.1

± 0.1 MHz) output SFDR for a

1.1 MHz fundamental output signal. System clock =

180 MHz (6

× REFCLK Multiplier engaged), V

S = +5 V.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2AP

40.1MHz

CENTER

200kHz

SPAN

20kHz/

RBW = 300Hz

VBW = 300Hz

SWT = 11.5s

RF ATT = 20dB

REF LVL = –7dBm

Figure 30. Narrowband (40.1

± 0.1 MHz) output SFDR for

a 40.1 MHz fundamental output signal. System clock =

180 MHz (6

× REFCLK Multiplier engaged), V

S = +5 V.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2AP

70.1MHz

CENTER

200kHz

SPAN

20kHz/

RBW = 300Hz

VBW = 300Hz

SWT = 11.5s

RF ATT = 20dB

REF LVL = –7dBm

Figure 31. Narrowband (70.1

± 0.1 MHz) output SFDR for

a 70.1 MHz fundamental output signal. System clock =

180 MHz (6

× REFCLK Multiplier engaged), V

S = +5 V.

Ch1 200mV

[]

Tek Run 4.00GS/s

Sample

M 12.5ns Ch 1

–200mV

D 200ps Runs After

: 208ps

@ : 1.940ns

Figure 32. Typical CMOS comparator p-p output jitter

with the AD9851 configured as a clock generator, DDS fOUT

= 10.1 MHz, VS = +5 V, system clock = 180 MHz, 70 MHz

LPF. Graph details the center portion of a rising edge with

scope in delayed trigger mode, 200 ps/div. Cursors show

208 ps p-p jitter.

Ch1 200mV

[]

Tek Run 4.00GS/s

Sample

M 12.5ns Ch 1

–200mV

D 200ps Runs After

: 204ps

@ : 3.672ns

Figure 33. Typical CMOS comparator p-p output jitter

with the AD9851 configured as a clock generator, DDS fOUT

= 40.1 MHz, VS = +5 V, system clock = 180 MHz, 70 MHz

LPF. Graph details the center portion of a rising edge with

scope in delayed trigger mode, 200 ps/div. Cursors show

204 ps p-p jitter.

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