AD9851 datasheet(3/23 Pages) AD

3 / 23 page

–3–

REV. C

AD9851

Test

AD9851BRS

Parameter

Temp

Level

Min

Typ

Max

Units

TIMING CHARACTERISTICS

tWH, tWL (W_CLK Min Pulsewidth High/Low)

FULL

3.5

tDS, tDH (Data to W_CLK Setup and Hold Times)

FULL

3.5

tFH, tFL (FQ_UD Min Pulsewidth High/Low)

FULL

tCD (REFCLK Delay After FQ_UD)

FULL

3.5

tFD (FQ_UD Min Delay After W_CLK)

FULL

tCF (Output Latency from FQ_UD)

Frequency Change

FULL

SYSCLK

Cycles

Phase Change

FULL

SYSCLK

Cycles

tRH (CLKIN Delay After RESET Rising Edge)

FULL

3.5

tRL (RESET Falling Edge After CLKIN)

FULL

3.5

tRR (Recovery from RESET)

FULL

SYSCLK

Cycles

tRS (Minimum RESET Width)

FULL

SYSCLK

Cycles

tOL (RESET Output Latency)

FULL

SYSCLK

Cycles

Wake-Up Time from Power-Down Mode

+25

°CV

µs

CMOS LOGIC INPUTS

Logic “1” Voltage, +5 V Supply

+25

°CI

3.5

Logic “1” Voltage, +3.3 V Supply

+25

°CI

3.0

Logic “1” Voltage, +2.7 V Supply

+25

°CI

2.4

Logic “0” Voltage

+25

°CI

0.4

Logic “1” Current

+25

°CI

µA

Logic “0” Current

+25

°CI

µA

Rise/Fall Time

+25

°C

100

Input Capacitance

+25

°CV

POWER SUPPLY

6 Current @:

62.5 MHz Clock, +2.7 V Supply

+25

°C

3035mA

100 MHz Clock, +2.7 V Supply

+25

°C

4050mA

62.5 MHz Clock, +3.3 V Supply

+25

°C

3545mA

125 MHz Clock, +3.3 V Supply

+25

°C

5570mA

62.5 MHz Clock, +5 V Supply

+25

°C

5065mA

125 MHz Clock, +5 V Supply

+25

°C

7090mA

180 MHz Clock, +5 V Supply

+25

°C

110

130

Power Dissipation @ :

62.5 MHz Clock, +5 V Supply

+25

°C

250

325

62.5 MHz Clock, +3.3 V Supply

+25

°C

115

150

62.5 MHz Clock, +2.7 V Supply

+25

°C

8595mW

100 MHz Clock, +2.7 V Supply

+25

°C

110

135

125 MHz Clock, +5 V Supply

+25

°C

365

450

125 MHz Clock, +3.3 V Supply

+25

°C

180

230

180 MHz Clock, +5 V Supply

+25

°C

555

650

PDISS Power-Down Mode @:

+5 V Supply

+25

°C

1755mW

+2.7 V Supply

+25

°CVI

NOTES

1+V

S collectively refers to the positive voltages applied to DVDD, PVCC and AVDD. Voltages applied to these pins should be of the same potential.

2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when

the clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.

3The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more

output jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic

signals (spur’s, noise), slower slew rate and low comparator overdrive.

4Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the Reference Clock; however, the presence of a Reference Clock is required to implement

those functions. In the absence of a Reference Clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable

until a Reference Clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the exter-

nal Reference Clock to assure proper timing.

5Not applicable when 6

× REFCLK Multiplier is engaged.

6Assumes no capacitive load on DACBP (Pin 17).

Specifications subject to change without notice.

AD9851 Datasheet(PDF) 3 Page - Analog Devices

AD9851 Datasheet(HTML) 3 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL