AD9851 datasheet(22/23 Pages) AD

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AD9851

–22–

REV. C

ANALOG OUTPUT FREQUENCY – MHz

070

110

120

VS = +3.3V

VS = +5V

100

Figure 40. Supply current variation with analog output

frequency at 180 MHz system clock (upper trace) and

125 MHz system clock (lower trace).

SYSTEM CLOCK – MHz

140

100

120

100

120

VS = +3.3V

VS = +5V

160

180

Figure 41. Supply current variation with system clock

frequency.

MAXIMUM DAC IOUT – mA

1.1MHz

40.1MHz

70.1MHz

Figure 42. Effect of DAC maximum output current on

wideband (0 to 72 MHz) SFDR at three representative DAC

output frequencies: 1.1 MHz, 40.1 MHz and 70.1 MHz. VS =

+5 V, 180 MHz system clock (6

× REFCLK Multiplier dis-

abled). Currents are set using appropriate values of RSET.

INPUT FREQUENCY – MHz

100

120

140

160

100

200

300

400

500

600

VS = +3.3V

VS = +5V

Figure 43. Minimum p-p input signal needed to toggle the

AD9851 comparator output. Comparator input is a sine

wave compared with a fixed voltage threshold. Use this

data in addition to sin(x)/x roll-off and any filter losses to

determine if adequate signal is being presented to the

AD9851 comparator.

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