AD9851 datasheet(21/23 Pages) AD

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AD9851

–21–

REV. C

Ch1 200mV

[]

Tek Run 4.00GS/s

Sample

: 280ps

@ : 2.668ns

M 12.5ns Ch 1

–200mV

D 200ps Runs After

Figure 34. Typical CMOS comparator p-p output jitter

with the AD9851 configured as a clock generator, DDS fOUT

= 70.1 MHz, VS = +5 V, system clock = 180 MHz, 70 MHz

LPF. Graph details the center portion of a rising edge with

scope in delayed trigger mode, 200 ps/div. Cursors show

280 ps p-p jitter.

FREQUENCY OFFSET – Hz

–145

100

10k

100k

–135

–130

–125

–120

–115

–100

AD9851 PHASE NOISE

–140

Figure 35. Output Phase Noise (5.2 MHz AOUT), 6 × REFCLK

Multiplier Enabled, System Clock = 180 MHz, Reference

Clock = 30 MHz

FREQUENCY OFFSET – Hz

–155

100

10k

100k

–145

–140

–135

–130

–125

–120

AD9851 RESIDUAL PHASE NOISE

–150

Figure 36. Output Residual Phase Noise (5.2 MHz AOUT),

× REFCLK Multiplier Disabled, System Clock = 180 MHz,

Reference Clock = 180 MHz

SYSTEM CLOCK FREQUENCY – MHz

100

120

140

160

180

VS = +3.3V

VS = +5V

FUNDAMENTAL OUTPUT =

SYSTEM CLOCK/3

Figure 37. Spurious-free dynamic range (SFDR) is gener-

ally a function of the DAC analog output frequency. Ana-

log output frequencies of 1/3 the system clock rate are

considered worst case. Plotted below are typical worst

case SFDR numbers for various system clock rates.

Ch1 100mV

[]

Tek Stop 2.50GS/s

22 Acgs

: 2.0ns

@ : 105.2ns

C1 Rise

2.03ns

M 20.0ns Ch 1

252mV

D 5.00ns Runs After

Figure 38. Comparator Rise Time, 15 pF Load

Ch1 100mV

[]

Tek Stop 2.50GS/s

2227 Acgs

: 2.3ns

@ : 103.6ns

C1 Fall

2.33ns

M 20.0ns Ch 1

252mV

D 5.00ns Runs After

Figure 39. Comparator Fall Time, 15 pF Load

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