AD9851 datasheet(11/23 Pages) AD

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AD9851

–11–

REV. C

Results of Reset, Figure 14

– Phase Accumulator zeroed such that the output = 0 Hertz

(dc).

– Phase Offset register set to zero such that DAC IOUT = Full-

Scale output and IOUTB = zero mA output.

– Internal Programming Address pointer reset to W0.

– Power-down bit reset to “0” (power-down disabled).

– 40-bit Data Input Register is NOT cleared.

–6

× Reference Clock multiplier is disabled.

– Parallel programming mode selected by default.

XXXXX10X

FQ UD

W CLK

SYSCLK

DAC

STROBE

DATA (W0)

INTERNAL CLOCKS

DISABLED

Figure 15. Parallel-Load Power-Down Sequence/Internal

Operation

XXXXX00X

FQ UD

W CLK

DATA (W0)

INTERNAL CLOCKS

ENABLED

SYSCLK

Figure 16. Parallel-Load Power-Up Sequence (to Recover

from Power-Down)/Internal Operation

SYSCLK

RESET

AOUT

tRS

tRH

tRL

tOL

COS (0 )

SYMBOL

DEFINITION

MIN SPEC

tRH

CLK DELAY AFTER RESET RISING EDGE 3.5ns*

tRL

RESET FALLING EDGE AFTER CLK

3.5ns*

tRR

RECOVERY FROM RESET

2 SYSCLK CYCLES

tRS

MINIMUM RESET WIDTH

5 SYSCLK CYCLES

tOL

RESET OUTPUT LATENCY

13 SYSCLK CYCLES

*SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED

tRR

Figure 14. Master Reset Timing Sequence

Entry to the serial mode, Figure 17, is via the parallel mode

which is selected by default after a RESET is asserted. One

needs only to program the first eight bits (word W0) with the

sequence xxxxx011 as shown in Figure 17 to change from paral-

lel to serial mode. The W0 programming word may be sent over

the 8-bit data bus or hardwired as shown in Figure 18. After

serial mode is achieved, the user must follow the programming

sequence of Figure 19.

XXXXX011

FQ UD

W CLK

DATA (W0)

ENABLE

SERIAL MODE

Figure 17. Serial-Load Enable Sequence

Note: After serial mode is invoked, it is best to immediately

write a valid 40-bit serial word (see Figure 19), even if it is all

zeros, followed by a FQ_UD rising edge to flush the “residual”

data left in the DDS core. A valid 40-bit serial word is any word

where W33 is Logic 0.

AD9851

10k

SUPPLY

Figure 18. Hardwired xxxxx011 Configuration for Serial-

Load Enable Word W0 in Figure 17

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