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PCM5142PW Datasheet(PDF) 32 Page - Texas Instruments |
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PCM5142PW Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 110 page  PCM5141, PCM5142 SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 13. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) (continued) SCK PLL VCO PLL REF DSP CLK MOD f fS (kHz) RSCK P M = K*R K = J.D R PLL FS DSP FS NMAC MOD fS NDAC DOSR % Error NCP CP f (kHz) (MHz) (MHz) (MHz) (MHz) (kHz) 48 1024 49.152 73.728 8 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 96 32 3.072 73.728 2 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 48 4.608 73.728 3 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 64 6.144 73.728 2 3.072 24 12 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 128 12.288 73.728 4 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 192 18.432 73.728 6 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 256 24.576 73.728 8 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 384 36.864 73.728 6 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 512 49.152 73.728 8 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536 192 32 6.144 73.728 2 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 48 9.216 73.728 3 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 64 12.288 73.728 4 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 128 24.576 73.728 8 3.072 24 24 1 384 192 2 36.864 32 6144 12 2 0 4 1536 192 192 36.864 73.728 6 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536 192 256 49.152 73.728 8 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536 384 32 12.288 73.728 2 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 48 18.432 73.728 3 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 64 24.576 73.728 4 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 128 49.152 73.728 8 6.144 12 12 1 192 96 2 36.864 16 6144 12 1 0 4 1536 32 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: PCM5141 PCM5142 |
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