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PCM5142PW Datasheet(PDF) 84 Page - Texas Instruments

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Part # PCM5142PW
Description  2VRMS DirectPath?? 112/106dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface
PDF  110 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCM5142PW Datasheet(HTML) 84 Page - Texas Instruments

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PCM5141, PCM5142
SLAS759A – AUGUST 2012 – REVISED SEPTEMBER 2012
www.ti.com
RSV
Reserved
Reserved. Do not access.
RBCK
Master Mode BCK Divider Reset
This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode BCK clock divider is reset
1: Master mode BCK clock divider is functional
RLRK
Master Mode LRCK Divider Reset
This bit, when set to 0, will reset the BCK divider to generate LRCK clock for I2S master mode. To use I2S
master mode, the divider must be enabled and programmed properly.
Default value: 0
0: Master mode LRCK clock divider is reset
1: Master mode LRCK clock divider is functional
Page 0 / Register 13
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
13
0D
RSV
RSV
RSV
SREF
RSV
RSV
RSV
RSV
Reset Value
0
RSV
Reserved
Reserved. Do not access.
SREF
PLL Reference
This bit select the source clock for internal PLL. This bit is ignored and overriden in clock auto set mode.
Default value: 0
0: The PLL reference clock is SCK
1: The PLL reference clock is BCK
Page 0 / Register 20
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
20
14
RSV
RSV
RSV
RSV
PPDV3
PPDV2
PPDV1
PPDV0
Reset Value
0
0
0
0
RSV
Reserved
Reserved. Do not access.
PPDV[3:0]
PLL P
These bits set the PLL divider P factor. These bits are ignored in clock auto set mode.
Default value: 0000
0000: P=1
0001: P=2
...
1110: P=15
1111: Prohibited (do not set this value)
Page 0 / Register 21
Dec
Hex
b7
b6
b5
b4
b3
b2
b1
b0
21
15
RSV
RSV
PJDV5
PJDV4
PJDV3
PJDV2
PJDV1
PJDV0
Reset Value
0
0
0
0
0
0
84
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: PCM5141 PCM5142



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