TLC5949 datasheet(40/51 Pages) TI

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'0'

See Note (2)

SID Data

Device Junction

Temperature (T )

LAT

OUTn

GSCLK

3 4

4093

4095

4094

4096

OFF

SCLK

'0'

TEF in SID

(Internal Data)

'0'

'1'

OFF

See Note (5)

See Note (6)

Old Latched GS Data

New Latched GS Data

First GS Data Latch

(Internal)

BLANK Bit

in First Control Data Latch

(Internal)

(1)

'1'

'0'

PTW in SID

(Internal Data)

'0'

'1'

T <

PTW

T ³

TEF

T ³

TEF

T ³

PTW

T <

TEF -

HYST

T ³

PTW

Write Data for First GS Latch

Common Shift Register

(Internal)

T <

PTW

See Note (4)

See Note (3)

TLC5949

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

www.ti.com

CURRENT REFERENCE (IREF PIN) SHORT FLAG (ISF)

The ISF function indicates that the IREF terminal is shorted with low impedance to GND. The ISF bit in the SID is

set to '1' during this condition. Then all outputs, OUTn, are forced off. See Table 15 for the ISF truth table.

PRE-THERMAL WARNING (PTW)

The PTW function indicates that the device junction temperature is high. The PTW in the SID is set to '1' while

the device junction temperature exceeds the temperature threshold (TPTW = +138°C, typ); however, the outputs

are not forced off. When the PTW is set, the device temperature should be reduced by lowering the power

dissipated in it to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished

by lowering the GS or BC data values. When the device junction temperature drops below the TPTW temperature,

the PTW bit in the SID is set to '0'. Figure 34 shows a timing diagram; see Table 15 for the PTW truth table.

(1) This internal signal is reset when LAT is input for a GS write with the display timing reset enabled.

(2) The PTW bit in SID is reset to '0' at the LAT rising edge for a GS data write if the device junction temperature is below tPTW.

(3) The PTW bit is set to '1' when the device junction temperature is greater than tPTW.

(4) The TEF bit in SID is reset to '0' at the LAT rising edge for a GS data write if the device junction temperature is below tTEF.

(5) OUT0 to OUT15 are forced off when TJ exceeds tTEF. Furthermore, the TEF bit is set to '1' at the same time.

(6) OUT0 to OUT15 are turned on at the first GSCLK rising edge if the device junction temperature is below tTEF with BLANK set to '0'.

Figure 34. PTW, TEF, and TSD Timing

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