TLC5949 datasheet(28/51 Pages) TI

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192 Bits

First Grayscale (GS) Data Latch (

Bits)

192

MSB

191

180

GS Data for OUT15

OUT15

Bit 15

OUT15

Bit 0

OUT3

Bit 0

OUT2

Bit 15

OUT2

Bit 0

GS Data for OUT2

OUT1

Bit 15

OUT1

Bit 0

GS Data for OUT1

LSB

OUT0

Bit 15

OUT0

Bit 0

GS Data for OUT0

192 Bits

Second Grayscale (GS) Data Latch (

Bits)

192

MSB

191

180

GS Data for OUT15

OUT15

Bit 15

OUT15

Bit 0

OUT3

Bit 0

OUT2

Bit 15

OUT2

Bit 0

GS Data for OUT2

OUT1

Bit 15

OUT1

Bit 0

GS Data for OUT1

LSB

OUT0

Bit 15

OUT0

Bit 0

GS Data for OUT0

192 Bits

To GS Timing Control Circuit

From Common Shift Register

This latch pulse comes

from the LAT pin when

the MSB of the Common

Shift Register is ‘0’.

The 4096th GSCLK is used

to latch the data when the

Auto Display Repeat is

enabled or when the BLANK bit

is set to ‘1’.

TLC5949

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

www.ti.com

193-Bit Common Shift Register

The 193-bit common shift register is used to shift data from the SIN pin into the TLC5949. The data shifted into

the register are used for GS and global BC functions. The common shift register LSB is connected to SIN and

the MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 193

bits are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered

up, the data in the 193-bit common shift register are random.

First and Second Grayscale (GS) Data Latch

The first and second GS data latches are each 192 bits long, and set the PWM timing for each constant-current

output. The on-time of all constant-current outputs is controlled by the data in the second GS data latch. A LAT

rising edge when the common shift register MSB is '0' shifts the least significant 192 bits of the common shift

4096th GSCLK occurs with the auto display repeat mode enabled, a LAT rising edge for a GS data write occurs

with the display timing reset mode enabled, or the BLANK bit in the first control data latch is set to '1'.

When the device is powered up, the data in the first and second latches are random. Therefore, GS data must

be written to the GS data latches before turning on the constant-current output. The first and second GS data

latch configurations are shown in Figure 28. The data bit assignment is shown in Table 5.

Figure 28. First and Second Grayscale Data Latch Configuration

Table 5. Grayscale Data Latch Bit Description

GS DATA LATCH BIT

CONTROLLED

GS DATA LATCH BIT

CONTROLLED

NUMBER

BIT NAME

CHANNEL

NUMBER

BIT NAME

CHANNEL

11-0

GSOUT0

Bits 11 to 0 for OUT0

107-96

GSOUT8

Bits 11 to 0 for OUT8

23-12

GSOUT1

Bits 11 to 0 for OUT1

119-108

GSOUT9

Bits 11 to 0 for OUT9

35-24

GSOUT2

Bits 11 to 0 for OUT2

131-120

GSOUT10

Bits 11 to 0 for OUT10

47-36

GSOUT3

Bits 11 to 0 for OUT3

143-132

GSOUT11

Bits 11 to 0 for OUT11

59-48

GSOUT4

Bits 11 to 0 for OUT4

155-144

GSOUT12

Bits 11 to 0 for OUT12

71-60

GSOUT5

Bits 11 to 0 for OUT5

167-156

GSOUT13

Bits 11 to 0 for OUT13

83-72

GSOUT6

Bits 11 to 0 for OUT6

179-168

GSOUT14

Bits 11 to 0 for OUT14

95-84

GSOUT7

Bits 11 to 0 for OUT7

191-180

GSOUT15

Bits 11 to 0 for OUT15

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