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LTC3890-2

38902f

OPERATION (Refer to the Functional Diagram)

A phase-locked loop (PLL) is available on the LTC3890-2

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3890-2’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of controller 1’s external top MOSFET to the ris-

ing edge of the synchronizing signal. Thus, the turn-on

of controller 2’s external top MOSFET is 180 degrees out

of phase to the rising edge of the external clock source.

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

The typical capture range of the phase-locked loop is from

approximately 55kHz to 1MHz, with a guarantee to be

between 75kHz and 850kHz. In other words, the LTC3890-

2’s PLL is guaranteed to lock to an external clock source

whose frequency is between 75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling).

When synchronized to an external clock using the PLLIN/

MODE pin, the LTC3890-2 operates in pulse-skipping

mode at light loads.

PolyPhase Applications (CLKOUT and PHASMD Pins)

The LTC3890-2 features two pins (CLKOUT and PHASMD)

that allow other controller ICs to be daisy-chained with the

LTC3890-2 in PolyPhase applications. The clock output

signal on the CLKOUT pin can be used to synchronize

additional power stages in a multiphase power supply

solution feeding a single, high current output or multiple

separate outputs. The PHASMD pin is used to adjust the

phase of the CLKOUT signal as well as the relative phases

between the two internal controllers, as summarized in

Table 1. The phases are calculated relative to the zero

degrees phase being defined as the rising edge of the top

gate driver output of controller 1 (TG1).

Table 1

VPHASMD

CONTROLLER 2 PHASE

CLKOUT PHASE

GND

180°

60°

Floating

180°

90°

INTVCC

240°

120°

Power Good (PGOOD1 and PGOOD2) Pins

Each PGOOD pin is connected to an open drain of an internal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD pin low when the corresponding VFB pin voltage is

not within ±10% of the 0.8V reference voltage. The PGOOD

pin is also pulled low when the corresponding RUN pin

is low (shut down). When the VFB pin voltage is within

the ±10% requirement, the MOSFET is turned off and the

pin is allowed to be pulled up by an external resistor to a

source no greater than 6V.

Theory and Benefits of 2-Phase Operation

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current flowing from the

input capacitor, requiring the use of more expensive input

capacitors and increasing both EMI and losses in the input

capacitor and battery.

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