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Z80C30 Datasheet(PDF) 75 Page - Zilog, Inc.

Part # Z80C30
Description  CMOS SCC Serial Communications Controller
PDF  81 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z80C30 Datasheet(HTML) 75 Page - Zilog, Inc.

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PS011706-0511
Electrical Characteristics
CMOS SCC Serial Communications Controller
Product Specification
67
Table 11. Z80C30 General Timing1
No
Symbol
Parameter
8MHz
10MHz
Min
Max
Min
Max
1TdPC(REQ)
PCLK Low to W/REQ Valid
250
200
2TsPC(W)
PCLK Low to Wait Inactive
350
300
3
TsRXC(PC)
RxC High to PCLK High Setup Time2,3
NA
NA
NA
NA
4
TsRXD(RXCr)
RxD to RxC High Setup Time
0
0
5
ThRXD(RxCr)
RxD to RxC High Hold Time2
150
125
6
TsRXD(RXCf)
RxD to RxC Low Setup Time2,4
0
0
7
ThRXD(RXCf)
RxD to RxC Low Hold Time2,4
150
125
8
TsSY(RXC)
SYNC to RxC High Setup Time2
-200
-150
9
ThSY(RXC)
SYNC to RxC High Hold Time2
5TcPc
5TcPc
10
TsTXC(PC)
TxC Low to PCLK High Setup Time3,5
NA
NA
11
TdTXCf(TXD)
TxC Low to TxD Delay5
190
150
12
TdTxCr(TXD)
TxC High to TxD Delay4,5
190
150
13
TdTXD(TRX)
TxD to TRxC Delay
200
140
14
TwRTXh
RTxC High Width6
130
120
15
TwRTXI
TRxC Low Width6
130
120
16a TcRTX
RTxC Cycle Time6,7
472
400
16b TxRx (DPLL)
DPLL Cycle Time Min7,8
59
50
17
TcRTXX
Crystal Osc. Period9
118
1000
100
1000
18
TwTRXh
TRxC High Width6
130
120
19
TwTRXI
TRxC Low Width6
130
120
20
TcTRX
TRxC Cycle Time6,7
472
400
21
TwEXT
DCD or CTS Pulse Width
200
120
22
TwSY
SYNC Pulse Width
200
120
Notes:
1. Units in nanoseconds (ns) otherwise noted.
2. RxC is RTxC or (TRxC, whichever is supplying the receive clock.
3. Synchronization of RxC to PCLK is eliminated in divide by four operation.
4. Parameter applies only to FM encoding/decoding.
5. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
6. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are
identical to case PCLK requirements.
7. The maximum receive or transmit data rate is 1/4 PCLK.
8. Applies to DPLL clock source oniy Maximum data rate of 1/4 PCLK still applies DPLL clock should have a 50%
duty cycle.
9. Both RTxC and SYNC have 30 pf capacitors to ground connected to them.



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