Z80C30 datasheet(46/81 Pages) ZILOG

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PS011706-0511

Functional Descriptions

CMOS SCC Serial Communications Controller

Product Specification

Z85C30 Timing

The SCC generates internal control signals from the WR and RD that are related to PCLK.

PCLK has no phase relationship with WR and RD, the circuitry generating the internal

control signals provides time for meta-stable conditions to disappear. This gives rise to a

recovery time related to PCLK. The recovery time applies only between bus transactions

involving the SCC.

The recovery time required for proper operation is specified from the falling edge of WR

or RD in the first transaction involving the SCC to the falling edge of WR or RD in the

second transaction involving the SCC. This time must be at least 3 PCLKs regardless of

which register or channel is being accessed.

The Z85C30 timings are described below:

• Read Cycle Timing

•

Write Cycle Timing

•

Interrupt Acknowledge Cycle Timing



Figure 20. Read Register Bit Functions

D7 D6 D5 D4 D3 D2 D1 D0

Read Register 13

TC8

TC9

TC10

TC11

TC12

TC13

TC14

TC15

Upper Byte

of Time Constant

D7 D6 D5 D4 D3 D2 D1 D0

Read Register 15

Zero Count IE

DCD IE

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

Break/Abort IE

Z80C30 Datasheet(PDF) 46 Page - Zilog, Inc.

Z80C30 Datasheet(HTML) 46 Page - Zilog, Inc.

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