Z80C30 datasheet(34/81 Pages) ZILOG

34 / 81 page

PS011706-0511

Functional Descriptions

CMOS SCC Serial Communications Controller

Product Specification

message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.

The byte count and status bits are accessed through Read Registers 6 and 7. Read Regis-

ters 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO

is separate from the 3-byte receive data FIFO.

Baud Rate Generator

Each channel in the SCC contains a programmable Baud Rate Generator (BRG). Each

generator consists of two 8-bit time constant registers that form a 16-bit time constant, a

16-bit down counter, and a flip-flop on the output producing a square wave. On startup,

the output flip-flop is set in a High state, the value in the time constant register is loaded

into the counter, and the counter starts counting down. The output of the BRG toggles

when reaching 0, the value in the time constant register is loaded into the counter, and the

process is repeated. The time constant can be changed at any time, but the new value does

not take effect until the next load of the counter.

The output of the BRG can be used as either the transmit clock, the receive clock, or both.

It can also drive the Digital Phase-locked loop (see Digital Phase-Locked Loop).

If the receive clock or transmit clock is not programmed to come from the TRxC pin, the

output of the BRG can be echoed out through the TRxC pin. The following formula relates

the time constant to the baud rate where PCLK or RTxC is the BRG input frequency in

Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7.

Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64.

Digital Phase-Locked Loop

The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information

from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is

nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with

the data stream, to construct a clock for the data. This clock is used as the SCC receive

clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source,

it provides a jitter-free clock output that is the DPLL input frequency divided by the

appropriate divisor for the selected encoding technique.

For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the

32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1

to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during

the next counting cycle), producing a terminal count closer to the center of the bit cell.

Time Constant =

PCLK or RTxC Frequency

2(Baud Rate)(Clock Mode)

-2

Z80C30 Datasheet(PDF) 34 Page - Zilog, Inc.