Z80C30 datasheet(30/81 Pages) ZILOG

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PS011706-0511

Functional Descriptions

CMOS SCC Serial Communications Controller

Product Specification

SCC Data Communications Capabilities

The SCC provides two independent full-duplex programmable channels for use in any

common asynchronous or synchronous data communication protocols; see Figure 9. Each

data communication channel has identical feature and capabilities.

Asynchronous Modes

Send and Receive is accomplished independently on each channel with five to eight bits

per character, plus optional even or odd parity. The transmitters can supply one, one-and-

a-half, or two stop bits per character and can provide a break output at any time. The

receiver break-detection logic interrupts the CPU both at the start and at the end of a

received break.

Reception is protected from spikes by a transient spike-rejection mechanism that checks

the signal one-half a bit time after a Low level is detected on the receive data input (RxDA

or RxDB pins). If the Low does not persist (a transient), the character assembly process

does not start.

Figure 9. SCC Protocols

Flag

Address

Information

CRC1

CRC2

Information

Flag

Data

SYNC

CRC1

Signal

CRC1

CRC2

Marking Line

Data

CRC2

SYNC

Data

CRC1

CRC2

SYNC

Data

Start

SDLC/HDLC/X.25

Parity

Stop

Data

Marking Line

External Sync

Bisync

Monosync

Asynchronous

Z80C30 Datasheet(PDF) 30 Page - Zilog, Inc.

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