82563EB datasheet(15/52 Pages) INTEL

15 / 52 page

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

3.7

Reset, Power Down, and Initialization Signals

3.8

JTAG and IEEE Interface

Table 6.

Reset and Power Down Signals

Signal Name

Type

Sub-

Type

Description

PHY_PWR_GOOD

TTL

Power Good (Power-On Reset)

The PHY_PWR_GOOD signal indicates good power is

available for The device. When set to 0b, the entire chip will be

held in a reset state.

PHY_RESET_N

TTL

Reset

When set to 0b, resets the device, including PHY and Kumeran

logic. Needs an external pull-up resistor if the signal isn’t

continuously being driven from an external source.

PHY_SLEEP

I (T)

TTL

Sleep / Power Down

This will power down the PHY and the Kumeran of both ports.

Needs an external pull-down resistor, if the signal isn’t

continuously being driven from an external source.

TEST_JTAG

I PU

TTL

Enable JTAG Pin Control

This pin should be pulled high through a 1 to 10 K

Ω 5% resistor

in normal operation.

Table 7.

JTAG Signals

Signal Name

Type

Sub-

Type

Description

JTAG_TCK

100

TTL

JTAG Clock

This pin should be pulled high through a 1 to 10 K

Ω 5% resistor

in normal operation.

JTAG_TDI

I PU

TTL

JTAG Serial Data Input

If not using JTAG, this pin may be pulled high through a 1 to

10 K

Ω 5% resistor

JTAG_TDO

TTL3

JTAG Serial Data Output

JTAG_TMS

I PU

TTL

JTAG TMS Input

If not using JTAG, this pin may be pulled high through a 1 to

10 K

Ω 5% resistor

82563EB Datasheet(PDF) 15 Page - Intel Corporation

82563EB Datasheet(HTML) 15 Page - Intel Corporation

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