82563EB datasheet(48/52 Pages) INTEL

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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

LEDA_ACTIVITY_N

LEDA_LINK_UP_N

DVDD

VDDO

MDIO

MDC

1 - 10 K

Ω, 5% p/d

MDIO_ADD[0]

1- 10 K

Ω, 5% p/d

MDIO_ADD[1]

1 - 10 K

Ω, 5% p/d

PHY_SLEEP

1 - 10 K

Ω, 5% p/d

PHY_RESET_N

1 - 10 K

Ω, 5% p/u

RESERVED_PD

1 - 10 K

Ω, 5% p/d

PHY_PWR_GOOD

RXB_MINUS

RESERVED_NC

RXB_PLUS

RESERVED_NC

AVDDF

TXB_MINUS

RESERVED_NC

TXB_PLUS

RESERVED_NC

VSS

TXA_PLUS,

TXA_MINUS

AVDDF

RXA_PLUS,

RXA_MINUS

TEST_JTAG

1 - 10 K

Ω, 5% p/u

PHY_CLK_OUT

VDDO

RESERVED_NC

JTAG_TDO

100

JTAG_TCK

1 - 10 K

Ω, 5%,p/d

Central

Pad

VSS

a. The 82564EB device uses the same name as the 82563EB device unless otherwise specified.

b. For those external strappings that state 1 - 10 K

Ω, 5%, the recommended value within that range

is 3.3 K

Ω, 5%.

Table 39. 82563EB/82564EB Pinout by Pin Number Order (Sheet 3 of 3)

82563EB

Dual Port

82564EB

Single Porta

External

Strappingb

82563EB Datasheet(PDF) 48 Page - Intel Corporation

82563EB Datasheet(HTML) 48 Page - Intel Corporation

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