82563EB datasheet(27/52 Pages) INTEL

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82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

Figure 3. 82563EB/82564EB power up sequencing with external regulators

4.4.2.2

External LVR Power down Sequencing

There are no specific power down sequencing and tracking requirements for the 82563EB/

82564EB silicon. The risk of latch-up or electrical overstress is small because only the charge

stored in the decoupling capacitors is left in the system.

4.4.3

Internally-Generated Power Delivery

The 82563EB/82564EB has two internal linear voltage regulator controllers. The controllers use

external transistors to generate 2 of the 3 required voltages: 1.9V (nominal) and 1.2V (nominal).

These two voltages are stepped-down from a 3.3V source.

3.3 V

1.2 V

Max

Difference

≤

0.5 V

1.9 V

Max

Difference

≤

0.5 V

Table 21. 3.3V External Power Supply Parameters

Title

Description

Min

Max

Units

Rise Time

Time from 10% to 90% mark

200

Monotonicity

Voltage dip allowed in ramp

300

Slope

Ramp rate at any given time between

10% and 90%

Min: 0.8*V(min)/Rise time (max)

Max: 0.8*V(max)/Rise time (min)

1500

mV/ms

Operational Range

Voltage range for normal operating

conditions

3.0

3.6

82563EB Datasheet(PDF) 27 Page - Intel Corporation

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