AMC7812 datasheet(9/92 Pages) TI

9 / 92 page

AMC7812

www.ti.com

SBAS513D – JANUARY 2011 – REVISED OCTOBER 2012

PIN DESCRIPTIONS

PIN (QFN / HTQFP)

DESCRIPTION

NO.

NAME

RESET

Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.

Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion

DAV

ends. In auto mode, a 1µs pulse (active low) appears on this pin when a conversion cycle finishes (see the

Primary ADC Operation and Registers sections for details). DAV stays high when deactivated.

CNVT

External conversion trigger, active low. The falling edge starts the sampling and conversion of the ADC.

Serial interface data. SDI for the serial peripheral interface (SPI) when the SPI/I2C pin is high. SDA for I2C

SDI/SDA

when the SPI/I2C pin is low.

Serial clock input of the main serial interface. SPI clock when the SPI/I2C pin is high; I2C clock when the

SCLK/SCL

SPI/I2C pin is low.

DGND

Digital ground

IOVDD

Interface power supply

DVDD

Digital power supply (+3V to +5V). Must be the same value as AVDD.

Chip select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I2C when the SPI/I2C

CS/A0

pin is low.

SDO/A1

SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I2C when the SPI/I2C pin is low.

Slave address selection A2 for I2C when the SPI/I2C pin is low.

Interface selection pin. Digital input. When this pin is tied to IOVDD, the SPI is enabled and the I

2C interface is

SPI/I2C

disabled. When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled.

GPIO-0

GPIO-1

General-purpose digital input/output. This pin is a bidirectional open-drain, digital input/output, and requires an

external pull-up resistor. See the General Purpose Input/Output Pins section for more details.

GPIO-2

GPIO-3

DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter

a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.

DAC-CLR-0

However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC

Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,

regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.

DAC5-OUT

DAC4-OUT

Output of DAC channels 3, 4, and 5

DAC3-OUT

AGND4

Analog ground

AGND3

Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, DAC5-OUT, must be

AVCC2

tied to AVCC1

DAC2-OUT

DAC1-OUT

Output of DAC channels 0, 1, and 2

DAC0-OUT

D2–/GPIO-6

Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pull-up required for output.

D2+/GPIO-7

Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pull-up required for output.

D1–/GPIO4

Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pull-up required for output.

D1+/GPIO-5

Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pull-up required for output.

External ADC reference input when external VREF is used to drive ADC. Compensation capacitor connection

ADC-REF-IN/CMP

(connect 4.7µF capacitor between this pin and AGND) when Internal VREF is used to drive ADC.

ADC-GND

ADC ground. Must be connected to AGND.

33-

Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be

CH0 to CH15

programmed as differential or single-ended.

AVDD1

Positive analog power supply

AVDD2

DAC6-OUT

DAC7-OUT

Output of DAC channels 6, 7, and 8

DAC8-OUT

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